公开(公告)号：US11569363B2

公开(公告)日：2023-01-31

申请号：US17192280

申请日：2021-03-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC分类号： H01L29/49 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768

摘要： In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US11527531B2

公开(公告)日：2022-12-13

申请号：US16412852

申请日：2019-05-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Hsiao-Chin Tuan ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Shi-Chuang Hsiao ,  Yu-Hong Kuo

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

摘要： In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

公开(公告)号：US11444169B2

公开(公告)日：2022-09-13

申请号：US16929640

申请日：2020-07-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Liang Chu ,  Chien-Chih Chou ,  Chih-Chang Cheng ,  Yi-Huan Chen ,  Kong-Beng Thei ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Ta-Yuan Kung

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L21/762

摘要： A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

公开(公告)号：US11011619B2

公开(公告)日：2021-05-18

申请号：US16562953

申请日：2019-09-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kong-Beng Thei ,  Chien-Chih Chou ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L29/78

摘要： In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

公开(公告)号：US10748899B2

公开(公告)日：2020-08-18

申请号：US15715541

申请日：2017-09-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

摘要： An integrated circuit having an epitaxial source and drain, which reduces gate burnout and increases switching speed so that is suitable for high voltage applications, is provided. The integrated circuit includes a semiconductor substrate having a high voltage N-well (HVNW) and a high voltage P-well (HVPW). The integrated circuit further includes a high-voltage device on the semiconductor substrate. The high-voltage device includes an epitaxial p-type source disposed in the HVNW, an epitaxial p-type drain disposed in the HVPW, and a gate arranged between the epitaxial p-type source and the epitaxial p-type drain on a surface of the semiconductor substrate.

公开(公告)号：US10553583B2

公开(公告)日：2020-02-04

申请号：US15688276

申请日：2017-08-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei

IPC分类号： H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423

摘要： The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.

公开(公告)号：US20200027845A1

公开(公告)日：2020-01-23

申请号：US16587819

申请日：2019-09-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC分类号： H01L23/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08

摘要： In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

公开(公告)号：US11410999B2

公开(公告)日：2022-08-09

申请号：US16797334

申请日：2020-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Ming Chyi Liu ,  Shih-Chung Hsiao ,  Jhih-Bin Chen

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/51 ,  H01P1/15 ,  H01L23/48

摘要： The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

公开(公告)号：US11133226B2

公开(公告)日：2021-09-28

申请号：US16169220

申请日：2018-10-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Hsiao-Chin Tuan ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Chia-Hong Wu

IPC分类号： H01L29/49 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/3105 ,  H01L29/08 ,  H01L27/092 ,  H01L29/45

摘要： Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.

公开(公告)号：US10804220B2

公开(公告)日：2020-10-13

申请号：US16587867

申请日：2019-09-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC分类号： H01L23/00 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10

摘要： In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.