公开(公告)号：US20170125594A1

公开(公告)日：2017-05-04

申请号：US14930231

申请日：2015-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L21/321 ,  H01L21/28 ,  H01L21/3105 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

公开(公告)号：US20170110567A1

公开(公告)日：2017-04-20

申请号：US15002287

申请日：2016-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN ,  Horng-Huei TSENG

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  G01N23/22 ,  H01L21/66 ,  H01L21/8234 ,  G01N23/225 ,  G01N21/21 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L29/785 ,  G01N2021/8848 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/67288 ,  H01L21/823431 ,  H01L21/823437 ,  H01L22/12 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795

Abstract: A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The method includes the steps of: forming a plurality of fins supported by a substrate; depositing a gate layer on the fins; and etching the gate layer by plasma etching with an etching gas to form a gate having two notch features. The etching gas is supplied at a ratio of a flow rate at a center area of the substrate to a flow rate at a periphery area of the substrate in a range from 0.2 to 1. The disclosure also provides a method of monitoring a quality of the FinFET device, the method comprising: measuring a profile of the notch feature; and obtaining the quality of the FinFET device by comparing the profile of the notch feature with a predetermined criterion.

公开(公告)号：US20160276340A1

公开(公告)日：2016-09-22

申请号：US14754627

申请日：2015-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN ,  Wei-Ting CHEN

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

Abstract translation: 半导体器件包括衬底，第一栅极，第二栅极和绝缘结构。 基板包括第一翅片和第二翅片。 第一个门被放置在第一个鳍上。 第二个门设置在第二个翅片上。 在第一栅极和第二栅极之间形成间隙，并且间隙朝向衬底变宽。 绝缘结构设置在间隙中。 绝缘结构具有彼此相对的顶表面和底表面。 底面朝向基板。 面向第一门的顶面的边​​缘在顶面向内弯曲。

公开(公告)号：US20150115363A1

公开(公告)日：2015-04-30

申请号：US14067424

申请日：2013-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Che-Cheng CHANG ,  Chang-Yin CHEN ,  Jr-Jung LIN ,  Chih-Han LIN ,  Yung-Jung CHANG

IPC: H01L27/12 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L27/1211 ,  H01L21/32137 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括衬底。 半导体器件还包括在衬底上的第一鳍和第二鳍。 半导体器件还包括分别在第一鳍片和第二鳍片上横穿的第一栅极电极和第二栅极电极。 此外，半导体器件包括在第一鳍片和第一栅极电极之间以及第二鳍片和第二栅极电极之间的栅极电介质层。 此外，半导体器件在衬底上包括虚拟栅电极，并且虚设栅极位于第一栅电极和第二栅电极之间。 虚拟栅电极的上部比虚拟栅电极的下部宽。

公开(公告)号：US20240258162A1

公开(公告)日：2024-08-01

申请号：US18593752

申请日：2024-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/528

CPC classification number: H01L21/76831 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L23/528 ,  H01L21/76804 ,  H01L23/485

Abstract: A device comprises a non-insulator structure, a dielectric layer, a metal via, a metal line, and a dielectric structure. The dielectric layer is over the non-insulator structure. The metal via is in a lower portion of the dielectric layer. The metal line is in an upper portion of the dielectric layer. The dielectric structure is embedded in a recessed region in the lower portion of the dielectric layer. The dielectric structure has a tapered top portion interfacing the metal via.

公开(公告)号：US20230387245A1

公开(公告)日：2023-11-30

申请号：US18232191

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Liang LU ,  Chang-Yin CHEN ,  Chih-Han LIN ,  Chia-Yang LIAO

IPC: H01L29/49 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823864 ,  H01L29/785 ,  H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L29/66545

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

公开(公告)号：US20220199413A1

公开(公告)日：2022-06-23

申请号：US17692824

申请日：2022-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: A method includes following steps. A substrate is etched using a hard mask as an etch mask to form a fin. A bottom anti-reflective coating (BARC) layer is over the fin. A recess is formed in the BARC layer to expose a first portion of the hard mask. A protective coating layer is formed at least on a sidewall of the recess in the BARC layer. A first etching step is performed to remove the first portion of the hard mask to expose a first portion of the fin, while leaving a second portion of the fin covered under the protective coating layer and the BARC layer. A second etching step is performed to lower a top surface of the first portion of the fin to below a top surface of the second portion of the fin.

公开(公告)号：US20200343355A1

公开(公告)日：2020-10-29

申请号：US16927958

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.

公开(公告)号：US20200321196A1

公开(公告)日：2020-10-08

申请号：US16908214

申请日：2020-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chang-Yin CHEN ,  Tung-Wen CHENG ,  Che-Cheng CHANG ,  Jr-Jung LIN ,  Chih-Han LIN

IPC: H01J37/32 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/78 ,  H01L21/67

Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.

公开(公告)号：US20200075766A1

公开(公告)日：2020-03-05

申请号：US16678637

申请日：2019-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng CHANG ,  Chih-Han LIN

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device is provided. The semiconductor device includes a gate stack over a semiconductor substrate. The gate stack has a work function layer and a gate dielectric layer, and tops of the work function layer and the gate dielectric layer are at different height levels. The semiconductor device also includes a protection element over the gate stack. The semiconductor device further includes a spacer extending along a side surface of the protection element and a sidewall of the gate stack.