公开(公告)号：US20230386913A1

公开(公告)日：2023-11-30

申请号：US18361770

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Yu-Ming Huang ,  Ethan Tseng ,  Ken-Yu Chang ,  Yi-Ying Liu

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L29/04 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76856 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.

公开(公告)号：US20230268173A1

公开(公告)日：2023-08-24

申请号：US18309298

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Min-Hsiu Hung ,  Chun-I Tsai ,  Ken-Yu Chang ,  Yi-Ying Liu

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02068 ,  H01L21/76877

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

公开(公告)号：US20230231025A1

公开(公告)日：2023-07-20

申请号：US17686055

申请日：2022-03-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Shahaji B. More ,  Yi-Ying Liu ,  Shuen-Shin Liang ,  Sung-Li Wang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/42392 ,  H01L21/762 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/66477 ,  H01L29/78696

Abstract: In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.

公开(公告)号：US11652149B2

公开(公告)日：2023-05-16

申请号：US17112782

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Hong-Ming Wu ,  Chen-Yuan Kao ,  Li-Hsiang Chao ,  Yi-Ying Liu

IPC: H01L29/417 ,  H01L29/40 ,  H01L23/538 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/41775 ,  H01L21/76859 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/5386 ,  H01L29/401

Abstract: A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.

公开(公告)号：US20220367660A1

公开(公告)日：2022-11-17

申请号：US17320553

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chih-Chien Chi ,  Chien-Shun Liao ,  Keng-Chu Lin ,  Kai-Ting Huang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang ,  Cheng-Wei Chang

IPC: H01L29/45 ,  H01L23/535 ,  H01L23/532 ,  H01L29/78 ,  H01L21/768

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

公开(公告)号：US11462471B2

公开(公告)日：2022-10-04

申请号：US16844133

申请日：2020-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Fang-Wei Lee

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

公开(公告)号：US11424185B2

公开(公告)日：2022-08-23

申请号：US16945595

申请日：2020-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Wei Chang ,  Chia-Hung Chu ,  Kao-Feng Lin ,  Hsu-Kai Chang ,  Shuen-Shin Liang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Po-Nan Yeh ,  Yu Shih Wang ,  U-Ting Chiu ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/285 ,  H01L21/02

Abstract: A semiconductor device includes a gate electrode, a source/drain structure, a lower contact contacting either of the gate electrode or the source/drain structure, and an upper contact disposed in an opening formed in an interlayer dielectric (ILD) layer and in direct contact with the lower contact. The upper contact is in direct contact with the ILD layer without an interposing conductive barrier layer, and the upper contact includes ruthenium.

公开(公告)号：US20220189825A1

公开(公告)日：2022-06-16

申请号：US17676638

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Yu-Ming Huang ,  Ethan Tseng ,  Ken-Yu Chang ,  Yi-Ying Liu

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L29/04 ,  H01L29/08 ,  H01L29/161 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, two semiconductor fins protruding from the substrate, an epitaxial feature over the two semiconductor fins and connected to the two semiconductor fins, a silicide layer over the epitaxial feature, a barrier layer over the silicide layer, and a metal layer over the barrier layer. The barrier layer includes a metal nitride. Along a boundary between the barrier layer and the metal layer, an atomic ratio of oxygen to metal nitride is about 0.15 to about 1.0.

公开(公告)号：US11282750B2

公开(公告)日：2022-03-22

申请号：US17010995

申请日：2020-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan Hsuan Hsu ,  I-Hsiu Wang ,  Yean-Zhaw Chen ,  Cheng-Wei Chang ,  Yu Shih Wang ,  Hsin-Yan Lu ,  Yi-Wei Chiu

IPC: H01L21/8234 ,  H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02 ,  H01L21/027 ,  H01L27/02 ,  H01L29/08 ,  H01L27/088

Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.

公开(公告)号：US20210358804A1

公开(公告)日：2021-11-18

申请号：US15931111

申请日：2020-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Yu-Ming Huang ,  Ethan Tseng ,  Ken-Yu Chang ,  Yi-Ying Liu

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/04 ,  H01L29/161 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66

Abstract: A method includes providing a structure that includes a semiconductor substrate, an epitaxial source/drain feature over the semiconductor substrate, and one or more dielectric layers over the epitaxial source/drain feature; etching a hole into the one or more dielectric layer to expose a portion of the epitaxial source/drain feature; forming a silicide layer over the portion of the epitaxial source/drain feature; forming a conductive barrier layer over the silicide layer; and applying a plasma cleaning process to at least the conductive barrier layer, wherein the plasma cleaning process uses a gas mixture including N2 gas and H2 gas and is performed at a temperature that is at least 300° C.