公开(公告)号：US20220173234A1

公开(公告)日：2022-06-02

申请号：US17108892

申请日：2020-12-01

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2 DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US11049960B2

公开(公告)日：2021-06-29

申请号：US16294687

申请日：2019-03-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Sameer Prakash Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L29/872 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L21/308 ,  H01L29/417 ,  H01L21/02

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US10707324B2

公开(公告)日：2020-07-07

申请号：US16456040

申请日：2019-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Dong Seup Lee ,  Jungwoo Joh ,  Naveen Tipirneni ,  Sameer Prakash Pendharkar

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L23/535 ,  H01L29/20 ,  H01L27/07 ,  H01L27/088

Abstract: One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.

公开(公告)号：US20150160285A1

公开(公告)日：2015-06-11

申请号：US14547849

申请日：2014-11-19

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Srikanth Krishnan ,  Sameer Pendharkar

IPC: G01R31/26 ,  H01L21/78 ,  H01L29/66 ,  H01L21/66

CPC classification number: G01R31/2621 ,  H01L29/2003 ,  H01L29/7787

Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.

Abstract translation: 一种方法包括将栅极脉冲发生器耦合到被测功率晶体管器件的栅极端子，将漏极脉冲发生器耦合到被测功率晶体管器件的漏极端子; 对于第一组测试条件，激活用于每个测试条件的漏极脉冲发生器以向漏极端施加电压脉冲，并且对于每个测试条件，向栅极端施加电压脉冲，门脉冲上升 仅在漏极脉冲下降到预定阈值以下之前; 对于第二组测试条件，向漏极端子施加电压脉冲，并向栅极端施加电压脉冲，漏极脉冲发生器和栅极脉冲发生器都处于活动状态，使得存在一些重叠; 并测量进入被测功率晶体管器件的漏极电流。 公开了一种装置。

公开(公告)号：US08916427B2

公开(公告)日：2014-12-23

申请号：US13886744

申请日：2013-05-03

Applicant: Texas Instruments Incorporated

Inventor： Asad Mahmood Haider ,  Jungwoo Joh

IPC: H01L21/338

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/66462

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract translation: 可以通过在半导体层上形成含硅栅极电介质层来形成半导体器件。 栅极金属层形成在栅极介质层上; 栅极金属层在形成期间包括2原子％至10原子％的硅。 栅极金属层被图案化以形成金属栅极。 随后形成源极和漏极接触孔，并在接触孔中形成接触金属并图案化。 随后的接触退火在至少750℃的温度下加热接触金属和栅极至少30秒。

公开(公告)号：US20250006593A1

公开(公告)日：2025-01-02

申请号：US18345939

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Hiroshi Yamasaki ,  Hisayuki Shimada ,  Kenichi Yoshikawa

IPC: H01L23/48 ,  H01L21/311 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L29/20

Abstract: A microelectronic device includes a semiconductor substrate with a III-N semiconductor layer over the semiconductor substrate. A substrate via opening extending through the III-N semiconductor layer and a substrate contact pad in the substrate via opening, contacting the semiconductor substrate provide a substrate contact. The microelectronic device also includes an inter-level dielectric layer with a planar surface over the substrate contact. The microelectronic device further includes an interconnect metal level over the inter-level dielectric layer. The substrate via opening is formed through the III-N semiconductor layer to expose the semiconductor substrate. The substrate contact pad is formed over the III-N semiconductor layer, extending into the substrate via opening and making contact with the semiconductor substrate, to form the substrate contact. The ILD layer is formed over the III-N semiconductor layer and the substrate contact pad, so that the ILD layer has a planar surface over the substrate via opening.

公开(公告)号：US12166119B2

公开(公告)日：2024-12-10

申请号：US18357431

申请日：2023-07-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20240322006A1

公开(公告)日：2024-09-26

申请号：US18189870

申请日：2023-03-24

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/7786

Abstract: A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of a GaN semiconductor material. The GaN FET includes a contact etch stop and a stretch contact electrically connecting a source region with the contact etch stop. The contact etch stop may stretch over a p-type GaN gate structure towards a drain region to form a field plate connected to the source region. The contact etch stop provides a method to connect the field plate to the source region which allows efficient area scaling of space between the source region and the p-GaN gate structure. Disclosed examples provide an associated process flow for forming such GaN FETs.

公开(公告)号：US12027468B2

公开(公告)日：2024-07-02

申请号：US17176995

申请日：2021-02-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo Joh ,  Young-Joon Park

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H05K1/02

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/53228 ,  H01L29/7816 ,  H05K1/0216

Abstract: A semiconductor device a strapped interconnect line, which in turn includes a first interconnect line at a first level above a semiconductor substrate, and a second interconnect line at a second level above the interconnect substrate. A dielectric capping layer is located directly on the first interconnect line. A plurality of strapping vias are connected between the first interconnect line and the second interconnect line. Each of the strapping vias extends from a first side of the first interconnect line to a second side of the second interconnect line.

公开(公告)号：US20230197784A1

公开(公告)日：2023-06-22

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L29/2003 ,  H01L29/0653

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.