公开(公告)号：US20240038580A1

公开(公告)日：2024-02-01

申请号：US17877976

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Hao Yang ,  Asad Haider ,  Guruvayurappan Mathur ,  Abbas Ali ,  Alexei Sadovnikov ,  Umamaheswari Aghoram

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L29/0623

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.

公开(公告)号：US20230298946A1

公开(公告)日：2023-09-21

申请号：US18148719

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Rajni J. Aggarwal ,  Steven J Adler

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/66 ,  H01L21/763

CPC classification number: H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L21/763

Abstract: An integrated circuit includes a bipolar transistor extending into a [100] surface of a semiconductor substrate having a crystalline lattice. A deep trench surrounds the bipolar transistor and has a path having a plurality of sides. At least one side extends in a direction parallel to a axis of the crystalline lattice.

公开(公告)号：US20230135889A1

公开(公告)日：2023-05-04

申请号：US17514786

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

IPC: H01L21/762 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming an integrated circuit forms a first oxygen diffusion barrier layer in a fixed position relative to a semiconductor substrate and forms an aperture through the first oxygen diffusion barrier layer to expose a portion of the semiconductor substrate. The method also forms a first LOCOS region in an area of the aperture and a second oxygen diffusion barrier layer along the first LOCOS region and along at least a sidewall portion of the first oxygen diffusion barrier layer in the area of the aperture. The method also deposits a polysilicon layer, at a temperature of 570° C. or less, over the second oxygen diffusion barrier layer, etches the polysilicon layer and the second oxygen diffusion barrier layer to form a spacer in the area of the aperture, and forms a second LOCOS region in the area of the aperture and aligned to the spacer.

公开(公告)号：US20230060695A1

公开(公告)日：2023-03-02

申请号：US17462880

申请日：2021-08-31

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Rajni J. Aggarwal ,  Steven J. Adler ,  Eugene C. Davis

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/265

Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

公开(公告)号：US11522043B2

公开(公告)日：2022-12-06

申请号：US17085116

申请日：2020-10-30

Applicant: Texas Instruments Incorporated

Inventor： Scott William Jessen ,  Tae Seung Kim ,  Steven Lee Prins ,  Can Duan ,  Abbas Ali ,  Erich Wesley Kinder

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/12 ,  H01L27/01 ,  H01L21/3213 ,  H01L21/311

Abstract: A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

公开(公告)号：US11195958B2

公开(公告)日：2021-12-07

申请号：US17023639

申请日：2020-09-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Binghua Hu ,  Alexei Sadovnikov ,  Abbas Ali ,  Yanbiao Pan ,  Stefan Herzer

IPC: H01L29/66 ,  H01L29/94 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

公开(公告)号：US10573553B2

公开(公告)日：2020-02-25

申请号：US16241143

申请日：2019-01-07

Applicant: Texas Instruments Incorporated

Inventor： Hong Yang ,  Abbas Ali ,  Yaping Chen ,  Chao Zuo ,  Seetharaman Sridhar ,  Yunlong Liu

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L23/532

Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

公开(公告)号：US10032663B1

公开(公告)日：2018-07-24

申请号：US15603856

申请日：2017-05-24

Applicant: Texas Instruments Incorporated

Inventor： Bradley David Sucher ,  Bernard John Fischer ,  Abbas Ali

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06

Abstract: A method for fabricating an integrated circuit (IC) includes etching trenches into a semiconductor surface of a substrate that has a mask thereon. Trench implanting using an angled implant then forms doped sidewalls of the trenches. Furnace annealing after trench implanting includes a ramp-up portion to a maximum peak temperature range of at least 975° C. and ramp-down portion, wherein the ramp-up portion is performed in a non-oxidizing ambient for at least a 100° C. temperature ramp portion with an O2 flow being less than 0.1 standard liter per minute (SLM). The sidewalls and a bottom of the trench are thermally oxidized to form a liner oxide after furnace annealing to form dielectric lined trenches. The dielectric lined trenches are filled with a fill material, and overburden portions of the fill material are then removed to form filled trenches.

公开(公告)号：US10002774B1

公开(公告)日：2018-06-19

申请号：US15697098

申请日：2017-09-06

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Young-Joon Park ,  Kyle McPherson

IPC: H01L21/44 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32136 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/53223

Abstract: A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is

公开(公告)号：US20170069708A1

公开(公告)日：2017-03-09

申请号：US15357796

申请日：2016-11-21

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Eric Beach

IPC: H01L49/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L28/24 ,  H01L21/7681 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

Abstract translation: 具有金属薄膜电阻器的集成电路，具有上覆蚀刻停止层。 一种通过添加一个光刻步骤在集成电路中形成金属薄膜电阻器的工艺。