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117 条记录 (耗时 0.037 秒)

    Integrated circuit having angled conductive feature
    31.
    发明授权
    Integrated circuit having angled conductive feature 有权

    公开(公告)号：US11024622B2

    公开(公告)日：2021-06-01

    申请号：US16722324

    申请日：2019-12-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Ting-Wei Chiang ,  Li-Chun Tien

    IPC分类号： H01L27/02 ,  G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  H01L23/528 ,  H01L27/092

    摘要： An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.

    Integrated circuit layout method, device, and system
    32.
    发明授权
    Integrated circuit layout method, device, and system 有权

    公开(公告)号：US10970451B2

    公开(公告)日：2021-04-06

    申请号：US16553958

    申请日：2019-08-28

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Jian-Sing Li ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Li-Chun Tien ,  Ting Yu Chen ,  Tzu-Ying Lin

    IPC分类号： G06F30/392 ,  H01L27/02

    摘要： A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.

    CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE
    38.
    发明申请
    CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件的接触结构

    公开(公告)号：US20160329405A1

    公开(公告)日：2016-11-10

    申请号：US15212969

    申请日：2016-07-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Kuo-Nan Yang ,  Ming-Hsiang Song ,  Ta-Pen Guo

    IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

    CPC分类号： H01L29/41775 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

    摘要： The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance.

    摘要翻译： 本发明涉及半导体器件的接触结构。 半导体器件的示例性结构包括在衬底上的绝缘区域; 绝缘区域上的栅极电极层，包括栅极中间线; 在与栅极电极层相邻的绝缘区域上的第一接触结构，包括第一中间线，其中第一中间线和栅极中间线具有第一距离; 以及在与包括第二中间线的第一接触结构相对的栅极电极层的一侧上的绝缘区域上的第二接触结构，其中第二中间线和栅极中间线具有大于第一距离的第二距离。

    Method of forming layout design
    40.
    发明授权
    Method of forming layout design 有权
    形成布局设计的方法

    公开(公告)号：US09336348B2

    公开(公告)日：2016-05-10

    申请号：US14484588

    申请日：2014-09-12

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Tung-Heng Hsieh ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Min-Hsiung Chiang ,  Ting-Wei Chiang ,  Li-Chun Tien

    IPC分类号： G06F17/50

    CPC分类号： H01L21/82345 ,  G06F17/5072 ,  H01L21/3043 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L29/66795

    摘要： A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

    摘要翻译： 公开了一种形成用于制造集成电路（IC）的布局设计的方法。 该方法包括识别由布局设计的多个门结构布局图案的一个或多个段所占据的布局设计中的一个或多个区域; 以及生成与所识别的一个或多个区域重叠的一组布局模式。 多个栅极结构布局图案具有比预定光刻技术的空间分辨率小的预定间距。 布置图案集合的第一布局图案具有小于预定间距的两倍的宽度。