知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

42 records (took 0.028 seconds)

    Electronic device using homomorphic encryption and encrypted data processing method thereof
    33.
    发明授权
    Electronic device using homomorphic encryption and encrypted data processing method thereof 有权

    公开(公告)号：US12170719B2

    公开(公告)日：2024-12-17

    申请号：US18379384

    申请日：2023-10-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-Young Jung ,  Jiyoup Kim ,  Changkyu Seol ,  Pilsang Yoon ,  Jinsoo Lim ,  Myunghoon Choi

    IPC: H04L9/00 ,  G06F21/32 ,  H04L9/08 ,  G06F21/60

    Abstract: An electronic device includes a memory storing data from an external source, an application processing unit (APU) transmitting a secret key and public key generation command, an isolated execution environment (IEE) generating a secret key in response to the secret key generation command, generating a public key based on the secret key in response to the public key generation command, and storing the secret key, and a non-volatile memory performing write and read operations depending on a request of the APU. When the data are stored in the memory, the APU transmits a public key request to the IEE and in response the IEE transfers the public key to the APU through a mailbox protocol. The APU generates a ciphertext by performing homomorphic encryption on the data based on an encryption key in the public key, and classifies and stores the public key and the ciphertext in the non-volatile memory.

    Circuit configured to compensate for timing skew and operation method thereof
    34.
    发明授权
    Circuit configured to compensate for timing skew and operation method thereof 有权

    公开(公告)号：US11929772B2

    公开(公告)日：2024-03-12

    申请号：US17490563

    申请日：2021-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changkyu Seol ,  Byung-Suk Woo ,  Sucheol Lee

    IPC: H04B1/10 ,  H04B1/00 ,  H04B17/21 ,  H04B17/29

    CPC classification number: H04B1/1018 ,  H04B1/0007 ,  H04B1/1027 ,  H04B17/21 ,  H04B17/29

    Abstract: An electronic circuit converts a receive signal being analog into reception data being digital. The electronic circuit includes a delay circuit that receives a first receive signal and outputs a reference signal, the reference signal being generated by delaying the first receive signal as much as one of a plurality of different timing delays respectively set to a plurality of loops, a sampler that receives a second receive signal and samples the second receive signal based on the reference signal in each of the plurality of loops, a timing skew estimation circuit that outputs a compensation signal for compensating for a timing skew by extracting a statistical characteristic of a plurality of sample data sampled through the sampler and estimating the timing skew based on the statistical characteristic, and a controller that controls an operation of the timing skew estimation circuit.

    Receiver performing background training, memory device including the same and method of receiving data using the same
    36.
    发明授权
    Receiver performing background training, memory device including the same and method of receiving data using the same 有权

    公开(公告)号：US11621871B2

    公开(公告)日：2023-04-04

    申请号：US17393811

    申请日：2021-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sucheol Lee ,  Changkyu Seol ,  Byungsuk Woo

    IPC: H04L25/03 ,  H04L27/00

    Abstract: A receiver included in a memory device includes a flag generator circuit, an equalizer circuit and an equalization controller circuit. The flag generator circuit is configured to, during a normal operation mode, generates a flag signal without an external command. The equalizer circuit is configured to, during the normal operation mode, receive an input data signal through a channel, generate an equalized signal by equalizing the input data signal based on an equalization coefficient, and generate a data sample signal including a plurality of data bits based on the equalized signal. The equalization controller circuit is configured to, during the normal operation mode, determine an amount of change in the equalization coefficient based on the flag signal, the equalized signal and the data sample signal, and perform a training operation in which the equalization coefficient is updated in real time based on the amount of change in the equalization coefficient.

    Neuromorphic package devices and neuromorphic computing systems
    37.
    发明授权
    Neuromorphic package devices and neuromorphic computing systems 有权

    公开(公告)号：US11620505B2

    公开(公告)日：2023-04-04

    申请号：US16881963

    申请日：2020-05-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Pilsang Yoon ,  Junghyun Hong

    IPC: G06N3/063 ,  G11C11/54 ,  G06N3/04 ,  G11C13/00

    Abstract: A neuromorphic package device includes a systolic array package and a controller. The systolic array package includes neuromorphic chips arranged in a systolic array along a first direction and a second direction. The controller communicates with a host controls the neuromorphic chips. Each of the neuromorphic chips sequentially transfers weights of a plurality layers of a neural network system in the first direction to store the weights. A first neuromorphic chip performs a calculation based on stored weights therein and an input data received in the second direction, and provides a result of the calculation to at least one of a second neuromorphic chip and a third neuromorphic chip which are adjacent to the first neuromorphic chip. The at least one of the second and third neuromorphic chips performs a calculation based on a provided result of the calculation and stored weights therein.

    RECEIVER RECEIVING MULTI-LEVEL SIGNAL, MEMORY DEVICE INCLUDING THE SAME AND METHOD OF RECEIVING DATA USING THE SAME
    38.
    发明申请
    RECEIVER RECEIVING MULTI-LEVEL SIGNAL, MEMORY DEVICE INCLUDING THE SAME AND METHOD OF RECEIVING DATA USING THE SAME 有权

    公开(公告)号：US20230033286A1

    公开(公告)日：2023-02-02

    申请号：US17962992

    申请日：2022-10-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsuk Woo ,  Sucheol Lee ,  Changkyu Seol

    IPC: G11C7/10 ,  G11C7/14 ,  G11C7/04

    Abstract: A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.

    Receiver receiving multi-level signal, memory device including the same and method of receiving data using ihe same
    39.
    发明授权
    Receiver receiving multi-level signal, memory device including the same and method of receiving data using ihe same 有权

    公开(公告)号：US11495271B2

    公开(公告)日：2022-11-08

    申请号：US17463635

    申请日：2021-09-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byungsuk Woo ,  Sucheol Lee ,  Changkyu Seol

    IPC: G11C7/10 ,  G11C7/14 ,  G11C7/04

    Abstract: A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.

    Storage device with artificial intelligence and storage system including the same
    40.
    发明授权
    Storage device with artificial intelligence and storage system including the same 有权

    公开(公告)号：US11468306B2

    公开(公告)日：2022-10-11

    申请号：US16906209

    申请日：2020-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehun Jang ,  Hongrak Son ,  Changkyu Seol ,  Hyejeong So ,  Hwaseok Oh ,  Pilsang Yoon ,  Jinsoo Lim

    IPC: G06N3/063 ,  G06F15/80 ,  G06F7/544 ,  G06N3/08

    Abstract: A storage system includes a host device and a storage device. The host device provides first input data for data storage function and second input data for artificial intelligence (AI) function. The storage device stores the first input data from the host device, and performs AI calculation based on the second input data to generate calculation result data. The storage device includes a first processor, a first nonvolatile memory, a second processor and a second nonvolatile memory. The first processor controls an operation of the storage device. The first nonvolatile memory stores the first input data. The second processor performs the AI calculation, and is distinguished from the first processor. The second nonvolatile memory stores weight data associated with the AI calculation, and is distinguished from the first nonvolatile memory.

Patent Agency Ranking