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    Radio frequency (RF) front end having multiple low noise amplifier modules
    33.
    发明授权
    Radio frequency (RF) front end having multiple low noise amplifier modules 有权
    射频（RF）前端具有多个低噪声放大器模块

    公开(公告)号：US09473336B2

    公开(公告)日：2016-10-18

    申请号：US14671939

    申请日：2015-03-27

    Applicant: QUALCOMM Incorporated

    Inventor： Dongling Pan ,  Aleksandar Miodrag Tasic ,  Rajagopalan Rangarajan ,  Lai Kan Leung ,  Chiewcharn Narathong ,  Yiwu Tang

    IPC: H04B7/00 ,  H04L27/06 ,  H04B1/10 ,  H04B7/26 ,  H04B1/00

    CPC classification number: H04L27/063 ,  H04B1/005 ,  H04B1/10 ,  H04B7/26

    Abstract: A radio frequency (RF) front end having multiple low noise amplifiers modules is disclosed. In an exemplary embodiment, an apparatus includes at least one first stage amplifier configured to amplify received carrier signals to generate at least one first stage carrier group. Each first stage carrier group includes a respective portion of the carrier signals. The apparatus also includes second stage amplifiers configured to amplify the first stage carrier groups. Each second stage amplifier configured to amplify a respective first stage carrier group to generate two second stage output signals that may be output to different demodulation stages where each demodulation stage demodulates a selected carrier signal.

    Abstract translation: 公开了具有多个低噪声放大器模块的射频（RF）前端。 在示例性实施例中，装置包括至少一个第一级放大器，其配置成放大接收的载波信号以产生至少一个第一级载波组。 每个第一级载波组包括载波信号的相应部分。 该装置还包括配置成放大第一级载波组的第二级放大器。 每个第二级放大器被配置为放大相应的第一级载波组以产生两个第二级输出信号，其可以被输出到不同的解调级，其中每个解调级解调所选择的载波信号。

    PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING
    36.
    发明申请
    PHASE-LOCKED LOOP USING DUAL LOOP MODE TO ACHIEVE FAST RESETTLING 审中-公开
    使用双循环模式的相位锁定环来实现快速重置

    公开(公告)号：US20140241335A1

    公开(公告)日：2014-08-28

    申请号：US13780968

    申请日：2013-02-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xinhua Chen ,  Yiwu Tang

    IPC: H03L7/06

    CPC classification number: H03L7/0891 ,  H03L7/093 ,  H03L7/107

    Abstract: A PLL operates in a first low bandwidth mode using a first control loop and in a second high bandwidth mode using a second control loop. The PLL includes a VCO that generates an output signal at a desired frequency used by a transmitter. When the transmitter switches from a High Power mode (HP TX) to a Low Power mode (LP TX), the PLL is perturbed (VCO no longer generates the desired frequency) and must resettle within an allocated time. In one example, the VCO frequency is 3.96 GHz and the settling time requirement is 25 microseconds. Upon switching from HP TX to LP TX, the PLL is switched to the second high bandwidth mode 15 microseconds and is then switched back to the first low bandwidth mode. The PLL resettles to within 1 ppm of the initial VCO frequency of 3.96 GHz within the allocated 25 microseconds.

    Abstract translation: PLL使用第一控制环路在第一低带宽模式下工作，并且在第二高带宽模式中使用第二控制环路工作。 PLL包括VCO，其产生以发射机使用的期望频率的输出信号。 当发射机从高功率模式（HP TX）切换到低功耗模式（LP TX）时，PLL被扰乱（VCO不再产生所需频率），并且必须在分配的时间内重新定位。 在一个示例中，VCO频率为3.96GHz，建立时间要求为25微秒。 从HP TX切换到LP TX时，PLL将切换到第二个高带宽模式15微秒，然后切换回第一个低带宽模式。 PLL在分配的25微秒内重置到3.96 GHz的初始VCO频率的1 ppm以内。

    Sampling phase-locked loop (PLL)
    39.
    发明授权
    Sampling phase-locked loop (PLL) 有权

    公开(公告)号：US09991897B1

    公开(公告)日：2018-06-05

    申请号：US15415201

    申请日：2017-01-25

    Applicant: QUALCOMM Incorporated

    Inventor： Dongmin Park ,  Jong Min Park ,  Yiwu Tang

    IPC: H03L7/08 ,  H03L7/091 ,  H03L7/099 ,  H04L7/033

    CPC classification number: H03L7/091 ,  H03L7/085 ,  H03L7/099 ,  H04L7/0331

    Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating oscillating signals. For example, certain aspects of the present disclosure provide a phase-locked loop (PLL) having a first switch coupled to a sampling input node of the PLL, an integrator coupled to an output of the sampling circuit, and a voltage-controlled oscillator (VCO) having an input coupled to an output of the integrator. In certain aspects, the PLL may also include a feedback path coupled to an output of the VCO and a control input of the first switch.

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