知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

39 records (took 0.025 seconds)

    Refresh scheme for memory cells with next bit table
    34.
    发明授权
    Refresh scheme for memory cells with next bit table 有权
    具有下一位表的存储单元的刷新方案

    公开(公告)号：US09230634B2

    公开(公告)日：2016-01-05

    申请号：US14276452

    申请日：2014-05-13

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Jungwon Suh ,  Xiangyu Dong

    IPC: G06F12/00 ,  G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0207 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

    Abstract: A memory refresh control technique allows flexible internal refresh rates based on an external 1× refresh rate and allows skipping a refresh cycle for strong memory rows based on the external 1× refresh rate. A memory controller performs a memory refresh by reading a refresh address from a refresh address counter, reading a weak address from a weak address table and generating a next weak address value based at least in part on a next bit sequence combined with the weak address. The memory controller compares the refresh address to the weak address and to the next weak address value. Based on the comparison, the memory controller selects between skipping a refresh cycle, refreshing the refresh address, refreshing the weak address, and refreshing both the refresh address and the weak address.

    Abstract translation: 存储器刷新控制技术允许基于外部1×刷新率的灵活的内部刷新率，并允许基于外部1×刷新率跳过强存储器行的刷新周期。 存储器控制器通过从刷新地址计数器读取刷新地址，从弱地址表读取弱地址并且至少部分地基于与弱地址组合的下一个比特序列产生下一个弱地址值来执行存储器刷新。 存储器控制器将刷新地址与弱地址和下一个弱地址值进行比较。 基于比较，存储器控制器在跳过刷新周期，刷新刷新地址，刷新弱地址以及刷新刷新地址和弱地址之间进行选择。

    PRIORITY ADJUSTMENT OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) TRANSACTIONS PRIOR TO ISSUING A PER-BANK REFRESH FOR REDUCING DRAM UNAVAILABILITY
    35.
    发明申请
    PRIORITY ADJUSTMENT OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) TRANSACTIONS PRIOR TO ISSUING A PER-BANK REFRESH FOR REDUCING DRAM UNAVAILABILITY 审中-公开
    优先调整动态随机存取存储器（DRAM）交易，以发布每次银行刷新以减少DRAM无法使用

    公开(公告)号：US20150318035A1

    公开(公告)日：2015-11-05

    申请号：US14267966

    申请日：2014-05-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G11C11/406

    CPC classification number: G06F13/1642

    Abstract: Priority adjustment of dynamic random access memory (DRAM) transactions prior to issuing a per-bank refresh for reducing DRAM unavailability is disclosed. In one aspect, DRAM is refreshed on a per-bank basis. If a queued memory transaction corresponds to a memory bank that will soon be refreshed, the transaction may be delayed if a refresh of the corresponding memory bank begins prior to execution of the transaction. To avoid delaying execution of the transaction while waiting for the corresponding memory bank to be refreshed, a priority of the memory transactions may be adjusted based on a memory bank refresh schedule. The priority of the transaction corresponding to the memory bank to be refreshed may be increased, and the priority of other memory transactions may be decreased, if such an adjustment would avoid or reduce delaying execution due to unavailability of the corresponding memory bank.

    Abstract translation: 公开了在发布用于减少DRAM不可用性的每存储体刷新之前的动态随机存取存储器（DRAM）事务的优先级调整。 在一个方面，DRAM以每个银行为基础刷新。 如果排队的存储器事务对应于将要刷新的存储体，则如果相应的存储体的刷新在执行事务之前开始，则事务可能被延迟。 为了避免在等待相应的存储体被刷新的同时执行事务的延迟，可以基于存储体刷新调度来调整存储器事务的优先级。 可以增加与要刷新的存储体对应的事务的优先级，并且如果这样的调整将避免或减少由于对应的存储体的不可用性而导致的延迟执行，则可以减少其他存储器事务的优先级。

    SYSTEM AND METHOD TO DEFRAGMENT A MEMORY
    36.
    发明申请
    SYSTEM AND METHOD TO DEFRAGMENT A MEMORY 有权
    限制存储器的系统和方法

    公开(公告)号：US20150186279A1

    公开(公告)日：2015-07-02

    申请号：US14146576

    申请日：2014-01-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F12/08

    CPC classification number: G06F12/0833 ,  G06F3/0608 ,  G06F12/0873 ,  G06F12/0895 ,  G06F12/12 ,  G06F2206/1004 ,  Y02D10/13

    Abstract: A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

    Abstract translation: 公开了一种用于对存储器进行碎片整理的系统和方法。 在特定实施例中，一种方法包括将存储在存储器的第一物理存储器地址上的数据从存储器加载到数据高速缓存的高速缓存行中。 第一个物理内存地址映射到第一个虚拟内存地址。 该方法还包括在数据高速缓存处启动与第一虚拟存储器地址相关联的查找信息的修改，使得第一虚拟存储器地址对应于存储器的第二物理存储器地址。 该方法还包括在数据高速缓存处修改与高速缓存行相关联的信息，以指示高速缓存线对应于第二物理存储器地址而不是第一物理存储器地址。

    CACHE STRUCTURE WITH PARITY-PROTECTED CLEAN DATA AND ECC-PROTECTED DIRTY DATA
    37.
    发明申请
    CACHE STRUCTURE WITH PARITY-PROTECTED CLEAN DATA AND ECC-PROTECTED DIRTY DATA 有权
    具有保密清洁数据和ECC保护的数据的缓存结构

    公开(公告)号：US20150149865A1

    公开(公告)日：2015-05-28

    申请号：US14090427

    申请日：2013-11-26

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F11/10

    CPC classification number: G06F11/1064 ,  G06F12/00

    Abstract: A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache.

    Abstract translation: 响应于确定数据是干净的，一种方法包括生成与要存储在高速缓存中的数据相关联的错误检测信息。 该方法还包括将清洁数据存储在高速缓存的第一区域。 响应于确定数据是脏的，该方法还包括生成与要存储在高速缓存中的数据相关联的纠错信息。 该方法还包括将脏数据存储在高速缓存的第二区域。

    INTER-SET WEAR-LEVELING FOR CACHES WITH LIMITED WRITE ENDURANCE
    38.
    发明申请
    INTER-SET WEAR-LEVELING FOR CACHES WITH LIMITED WRITE ENDURANCE 有权
    具有有限写入耐力的缓存的相互冲击

    公开(公告)号：US20140237160A1

    公开(公告)日：2014-08-21

    申请号：US13772400

    申请日：2013-02-21

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xiangyu Dong

    IPC: G06F12/02 ,  G06F12/08

    CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/0891 ,  G06F2212/7211

    Abstract: A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N2−N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.

    Abstract translation: 高速缓存控制器包括第一寄存器，其在每个存储器位置交换操作之后更新高速缓冲存储器中的多个高速缓存组并且重置每个N-1个存储器位置交换操作。 N是高速缓冲存储器中的多个缓存集合。 存储器控制器还具有在每N-1个存储器位置交换操作之后更新的第二寄存器，并且重置每个（N2-N）个存储器位置交换操作。 第一和第二寄存器跟踪高速缓存集合的逻辑位置和物理位置之间的关系。

    HETEROGENEOUS MEMORY SYSTEMS, AND RELATED METHODS AND COMPUTER-READABLE MEDIA FOR SUPPORTING HETEROGENEOUS MEMORY ACCESS REQUESTS IN PROCESSOR-BASED SYSTEMS
    39.
    发明申请
    HETEROGENEOUS MEMORY SYSTEMS, AND RELATED METHODS AND COMPUTER-READABLE MEDIA FOR SUPPORTING HETEROGENEOUS MEMORY ACCESS REQUESTS IN PROCESSOR-BASED SYSTEMS 有权
    异构存储器系统以及相关方法和计算机可读介质，用于支持基于处理器的系统中的异构存储器访问请求

    公开(公告)号：US20140201435A1

    公开(公告)日：2014-07-17

    申请号：US13743400

    申请日：2013-01-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G11C11/406 ,  G06F12/08

    CPC classification number: G11C11/40603 ,  G06F12/08 ,  G06F13/1694 ,  Y02D10/14

    Abstract: Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

    Abstract translation: 公开了用于在基于处理器的系统中支持异构存储器访问请求的异构存储器系统以及相关方法和计算机可读介质。 异构存储器系统由可以针对给定存储器访问请求访问的多个均匀存储器组成。 每个均匀存储器具有特定的功率和性能特性。 在这方面，存储器访问请求可以有利地基于存储器访问请求以及功率和/或性能考虑路由到异构存储器系统中的同构存储器之一。 作为非限制性示例，异类存储器访问请求策略可以基于诸如读/写类型，页面命中的频率和存储器流量的关键操作参数动态地预定义或确定。 以这种方式，存储器访问请求时间可以被优化以被减少，而不需要进行与仅具有可用于存储的一个存储器类型相关联的权衡。

Patent Agency Ranking