公开(公告)号：US20160055094A1

公开(公告)日：2016-02-25

申请号：US14462773

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Ali Iranli ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.

Abstract translation: 方面包括计算设备，系统和方法，用于对小于高速缓存线的数据实现高速缓冲存储器访问请求，并且通过将数据与高速缓存行的大小之间的差大小的填充数据组合来消除从主存储器的超时 和数据。 处理器可以使用数据的大小或数据的压缩比来确定未压缩或压缩的数据是否小于高速缓存行。 处理器可以使用恒定的数据值或数据值的模式来生成填充数据。 处理器可以将组合数据的写高速缓存存储器访问请求发送到高速缓冲存储器控制器，高速缓冲存储器控制器可以将组合的数据写入高速缓冲存储器。 高速缓冲存储器控制器可以将写存储器访问请求发送到存储器控制器，存储器控制器可以将组合的数据写入存储器。

公开(公告)号：US20160055093A1

公开(公告)日：2016-02-25

申请号：US14462763

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0866 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by writing supplemental data to the unfilled portions of the cache line. A cache memory controller may receive a cache memory access request with a supplemental write command for data smaller than a cache line. The cache memory controller may write supplemental to the portions of the cache line not filled by the data in response to a write cache memory access request or a cache miss during a read cache memory access request. In the event of a cache miss, the cache memory controller may retrieve the data from the main memory, excluding any overfetch data, and write the data and the supplemental data to the cache line. Eliminating overfetching reduces bandwidth and power required to retrieved data from main memory.

Abstract translation: 方面包括用于对小于高速缓存线的数据实现高速缓冲存储器访问请求的计算设备，系统和方法，并且通过将补充数据写入到高速缓存行的未填充部分来消除从主存储器的超时。 高速缓存存储器控制器可以接收具有小于高速缓存线的数据的补充写入命令的高速缓存存储器访问请求。 高速缓冲存储器控制器可以在读取高速缓存存储器访问请求期间响应于写入高速缓存存储器访问请求或高速缓存未命中而对未被数据填充的高速缓存行的部分进行补充。 在高速缓存未命中的情况下，高速缓存存储器控制器可以从主存储器检索数据，排除任何过采取数据，并将数据和补充数据写入高速缓存行。 消除过载减少从主存储器检索数据所需的带宽和功率。

公开(公告)号：US20160041905A1

公开(公告)日：2016-02-11

申请号：US14451639

申请日：2014-08-05

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

公开(公告)号：US20140181542A1

公开(公告)日：2014-06-26

申请号：US14174012

申请日：2014-02-06

Applicant: QUALCOMM Incorporated

Inventor： Sumit Sur ,  Bohuslav Rychlik ,  Steven S. Thomson ,  Ali Iranli ,  Brian J. Salsbery

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/24

Abstract: A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

Abstract translation: 公开了一种在多核中央处理单元（CPU）内控制功率的方法。 该方法可以包括监视模具温度，确定CPU的工作负载内的并行程度，以及基于平行度，模具温度或其组合来向上或向下驱动CPU的一个或多个核心。

公开(公告)号：US20130151879A1

公开(公告)日：2013-06-13

申请号：US13759709

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman S. Gargash

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案的方法，系统和设备，用于为一组处理器计算和实施性能保证，以确保处理器不处于忙状态（例如，由于临时工作负载） 该组合时段大于超过一个处理器完成其预先计算的稳态工作量所需的预定时间量。 DCVS可以基于可变延迟来调整一个或多个处理器的频率和/或电压，以确保多处理器系统仅落后于其稳态工作负载，最多只能达到预定的最大工作量，而不管 处理器的工作频率或电压。

公开(公告)号：US20240326867A1

公开(公告)日：2024-10-03

申请号：US18193912

申请日：2023-03-31

Applicant: QUALCOMM Incorporated

Inventor： Sriram Hariharan ,  Bohuslav Rychlik ,  Deepak Baranwal ,  Vinay Kumar Garipelli ,  Amod Phadke

IPC: B60W60/00 ,  B60W50/04 ,  G07C5/00

CPC classification number: B60W60/0015 ,  B60W50/045 ,  G07C5/008 ,  B60W2050/046

Abstract: A processor-based system employing a safety island architecture for fail-safe operation and related methods are disclosed. The processor-based system includes a main domain for controlling a device. The main domain receives and processes vehicle information from a vehicle network. The main domain communicates with vehicle modules to control operation of the vehicle. Such operation may include different autonomous driving use cases. The processing system includes a safety island domain that includes less hardware circuits as in the main domain. The safety island domain is configured to checkpoint vehicle information processed by both the main and safety island domains and to monitor errors originating in both the main and safety island.

公开(公告)号：US11016898B2

公开(公告)日：2021-05-25

申请号：US16543328

申请日：2019-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik ,  Wesley James Holland ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0868 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/1072

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

公开(公告)号：US10747671B1

公开(公告)日：2020-08-18

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06T1/60 ,  G06F12/0862 ,  G06F12/1009

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

公开(公告)号：US10386904B2

公开(公告)日：2019-08-20

申请号：US15086054

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Christophe Denis Bernard Avoinne ,  Manokanthan Somasundaram ,  Sina Dena ,  Paul Christopher John Wiercienski ,  Bohuslav Rychlik ,  Steven John Halter ,  Jaya Prakash Subramaniam Ganasan ,  Myil Ramkumar ,  Dipti Ranjan Pal

IPC: G06F1/26 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F12/08

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

公开(公告)号：US10261910B2

公开(公告)日：2019-04-16

申请号：US15077534

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/0802 ,  G06F12/0875 ,  G06F12/0886

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.