公开(公告)号：US09858196B2

公开(公告)日：2018-01-02

申请号：US14462773

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Ali Iranli ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0886 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0893 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.

公开(公告)号：US09086877B2

公开(公告)日：2015-07-21

申请号：US13668764

申请日：2012-11-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Khan

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract translation: 公开了实时监控一个或多个中央处理单元的装置和方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。 设备可以包括用于实时监视与一个或多个CPU相关联的状态数据的装置，用于过滤状态数据的装置，以及用于至少部分地基于经过滤的状态数据选择性地改变一个或多个系统设置的装置。 设备还可以包括子采样电路，其被配置为从中央处理单元接收硬件核心信号并输出​​中央处理单元状态指示，以及无限脉冲响应滤波器，连接到子采样电路并被配置为接收中央 来自子采样电路的处理单元状态指示。

公开(公告)号：US09081558B2

公开(公告)日：2015-07-14

申请号：US14174012

申请日：2014-02-06

Applicant: QUALCOMM Incorporated

Inventor： Sumit Sur ,  Bohuslav Rychlik ,  Steven S. Thomson ,  Ali Iranli ,  Brian J. Salsbery

IPC: G06F1/26 ,  G06F1/20 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/24

Abstract: A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

Abstract translation: 公开了一种在多核中央处理单元（CPU）内控制功率的方法。 该方法可以包括监视模具温度，确定CPU的工作负载内的并行程度，以及基于平行度，模具温度或其组合来向上或向下驱动CPU的一个或多个核心。

公开(公告)号：US09176572B2

公开(公告)日：2015-11-03

申请号：US13759709

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman S. Gargash

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案的方法，系统和设备，用于为一组处理器计算和实施性能保证，以确保处理器不处于忙状态（例如，由于临时工作负载） 该组合时段大于超过一个处理器完成其预先计算的稳态工作量所需的预定时间量。 DCVS可以基于可变延迟来调整一个或多个处理器的频率和/或电压，以确保多处理器系统仅落后于其稳态工作负载，最多只能达到预定的最大工作量，而不管 处理器的工作频率或电压。

公开(公告)号：US20130061069A1

公开(公告)日：2013-03-07

申请号：US13668764

申请日：2012-11-05

Applicant: Qualcomm Incorporated

Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Khan

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Devices and methods for monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract translation: 公开了用于实时监控一个或多个中央处理单元的装置和方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。 设备可以包括用于实时监视与一个或多个CPU相关联的状态数据的装置，用于过滤状态数据的装置，以及用于至少部分地基于经过滤的状态数据选择性地改变一个或多个系统设置的装置。 设备还可以包括子采样电路，其被配置为从中央处理单元接收硬件核心信号并输出​​中央处理单元状态指示，以及无限脉冲响应滤波器，连接到子采样电路并被配置为接收中央 来自子采样电路的处理单元状态指示。

公开(公告)号：US20160055094A1

公开(公告)日：2016-02-25

申请号：US14462773

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Ali Iranli ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0893 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.

Abstract translation: 方面包括计算设备，系统和方法，用于对小于高速缓存线的数据实现高速缓冲存储器访问请求，并且通过将数据与高速缓存行的大小之间的差大小的填充数据组合来消除从主存储器的超时 和数据。 处理器可以使用数据的大小或数据的压缩比来确定未压缩或压缩的数据是否小于高速缓存行。 处理器可以使用恒定的数据值或数据值的模式来生成填充数据。 处理器可以将组合数据的写高速缓存存储器访问请求发送到高速缓冲存储器控制器，高速缓冲存储器控制器可以将组合的数据写入高速缓冲存储器。 高速缓冲存储器控制器可以将写存储器访问请求发送到存储器控制器，存储器控制器可以将组合的数据写入存储器。

公开(公告)号：US20140181542A1

公开(公告)日：2014-06-26

申请号：US14174012

申请日：2014-02-06

Applicant: QUALCOMM Incorporated

Inventor： Sumit Sur ,  Bohuslav Rychlik ,  Steven S. Thomson ,  Ali Iranli ,  Brian J. Salsbery

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/24

Abstract: A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

Abstract translation: 公开了一种在多核中央处理单元（CPU）内控制功率的方法。 该方法可以包括监视模具温度，确定CPU的工作负载内的并行程度，以及基于平行度，模具温度或其组合来向上或向下驱动CPU的一个或多个核心。

公开(公告)号：US20130151879A1

公开(公告)日：2013-06-13

申请号：US13759709

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman S. Gargash

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案的方法，系统和设备，用于为一组处理器计算和实施性能保证，以确保处理器不处于忙状态（例如，由于临时工作负载） 该组合时段大于超过一个处理器完成其预先计算的稳态工作量所需的预定时间量。 DCVS可以基于可变延迟来调整一个或多个处理器的频率和/或电压，以确保多处理器系统仅落后于其稳态工作负载，最多只能达到预定的最大工作量，而不管 处理器的工作频率或电压。

公开(公告)号：US09104411B2

公开(公告)日：2015-08-11

申请号：US13669043

申请日：2012-11-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman Scott Gargash

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F9/50

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案，方案，系统和设备，配置为计算和实施性能保证，以确保处理器不处于忙碌状态（例如，由于临时工作负载）超过预定量 的时间高于该处理器完成其预先计算的稳态工作负载所需的时间。 DCVS可以基于可变延迟来调整处理器的频率和/或电压，以确保处理核心仅在最大程度上预定的最大工作量之下落在其稳态工作负载之后，而与工作频率或电压无关 的处理器。

公开(公告)号：US20130074085A1

公开(公告)日：2013-03-21

申请号：US13669043

申请日：2012-11-05

Applicant: Qualcomm Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman S. Gargash

IPC: G06F1/08 ,  G06F9/46

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案，方案，系统和设备，配置为计算和实施性能保证，以确保处理器不处于忙碌状态（例如，由于临时工作负载）超过预定量 的时间高于该处理器完成其预先计算的稳态工作负载所需的时间。 DCVS可以基于可变延迟来调整处理器的频率和/或电压，以确保处理核心仅在最大程度上预定的最大工作量之下落在其稳态工作负载之后，而与工作频率或电压无关 的处理器。