公开(公告)号：US09176572B2

公开(公告)日：2015-11-03

申请号：US13759709

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman S. Gargash

IPC: G06F1/32

CPC classification number: G06F1/329 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案的方法，系统和设备，用于为一组处理器计算和实施性能保证，以确保处理器不处于忙状态（例如，由于临时工作负载） 该组合时段大于超过一个处理器完成其预先计算的稳态工作量所需的预定时间量。 DCVS可以基于可变延迟来调整一个或多个处理器的频率和/或电压，以确保多处理器系统仅落后于其稳态工作负载，最多只能达到预定的最大工作量，而不管 处理器的工作频率或电压。

公开(公告)号：US20130061069A1

公开(公告)日：2013-03-07

申请号：US13668764

申请日：2012-11-05

Applicant: Qualcomm Incorporated

Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Khan

IPC: G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Devices and methods for monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract translation: 公开了用于实时监控一个或多个中央处理单元的装置和方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。 设备可以包括用于实时监视与一个或多个CPU相关联的状态数据的装置，用于过滤状态数据的装置，以及用于至少部分地基于经过滤的状态数据选择性地改变一个或多个系统设置的装置。 设备还可以包括子采样电路，其被配置为从中央处理单元接收硬件核心信号并输出​​中央处理单元状态指示，以及无限脉冲响应滤波器，连接到子采样电路并被配置为接收中央 来自子采样电路的处理单元状态指示。

公开(公告)号：US09690708B2

公开(公告)日：2017-06-27

申请号：US14716077

申请日：2015-05-19

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Bohuslav Rychlik ,  Steven S. Thomson

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0864 ,  G06F12/0802 ,  G06F17/50 ,  G06F12/0811 ,  G06F12/1027

CPC classification number: G06F12/0864 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/1027 ,  G06F17/5022 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/684

Abstract: Systems and methods for forecasting behavior of caches include a hypothetical cache. The hypothetical cache is configured to emulate cache behavior, and performance metrics for the hypothetical cache are determined, where the performance metrics may be based on cache hits/misses. Performance metrics for a real cache of a processor core of a processing system may also be similarly determined. Behavior of the real cache is forecast based, at least, on performance metrics of the hypothetical cache, and in some cases, also on performance metrics of the real cache (e.g., based on a comparison of the performance metrics). Actions may be recommended and/or performed based on the forecast, where the actions include modifying the real cache size, associativity, or allocation for processor cores, migrating a task running in one processor cluster to another processor cluster, or for collecting data for the real cache for offline analysis.

公开(公告)号：US09086877B2

公开(公告)日：2015-07-21

申请号：US13668764

申请日：2012-11-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Ali Iranli ,  Michael J. Drop ,  Vinodh R. Cuppu ,  Christopher Kong Yee Chun ,  Tao Xue ,  Haw-Jing Lo ,  Moinul H. Khan

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

Abstract translation: 公开了实时监控一个或多个中央处理单元的装置和方法。 该方法可以包括：实时地监视与一个或多个CPU相关联的状态数据，过滤状态数据，并且至少部分地基于经过滤的状态数据，选择性地改变一个或多个系统设置。 设备可以包括用于实时监视与一个或多个CPU相关联的状态数据的装置，用于过滤状态数据的装置，以及用于至少部分地基于经过滤的状态数据选择性地改变一个或多个系统设置的装置。 设备还可以包括子采样电路，其被配置为从中央处理单元接收硬件核心信号并输出​​中央处理单元状态指示，以及无限脉冲响应滤波器，连接到子采样电路并被配置为接收中央 来自子采样电路的处理单元状态指示。

公开(公告)号：US09081558B2

公开(公告)日：2015-07-14

申请号：US14174012

申请日：2014-02-06

Applicant: QUALCOMM Incorporated

Inventor： Sumit Sur ,  Bohuslav Rychlik ,  Steven S. Thomson ,  Ali Iranli ,  Brian J. Salsbery

IPC: G06F1/26 ,  G06F1/20 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/24

Abstract: A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

Abstract translation: 公开了一种在多核中央处理单元（CPU）内控制功率的方法。 该方法可以包括监视模具温度，确定CPU的工作负载内的并行程度，以及基于平行度，模具温度或其组合来向上或向下驱动CPU的一个或多个核心。

公开(公告)号：US09104411B2

公开(公告)日：2015-08-11

申请号：US13669043

申请日：2012-11-05

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman Scott Gargash

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F9/50

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案，方案，系统和设备，配置为计算和实施性能保证，以确保处理器不处于忙碌状态（例如，由于临时工作负载）超过预定量 的时间高于该处理器完成其预先计算的稳态工作负载所需的时间。 DCVS可以基于可变延迟来调整处理器的频率和/或电压，以确保处理核心仅在最大程度上预定的最大工作量之下落在其稳态工作负载之后，而与工作频率或电压无关 的处理器。

公开(公告)号：US20140002730A1

公开(公告)日：2014-01-02

申请号：US13929614

申请日：2013-06-27

Applicant: QUALCOMM Incorporated

Inventor： Steven S. Thomson ,  Mriganka Mondal ,  Nishant Hariharan ,  Edoardo Regini

IPC: H04N7/01

CPC classification number: H04N7/0127 ,  G06F1/3206 ,  G06F1/3265 ,  Y02D10/153

Abstract: The present disclosure provides for systems, methods, and apparatus for image processing. These systems, methods, and apparatus may compare a current frame to at least one previous frame to determine an amount of difference. The amount of difference between the current frame and the at least one previous frame may be compared to a threshold value. Additionally, the frame rate may be adjusted based on the comparison of the amount of difference between the current frame and the at least one previous frame and the threshold value. Another example may determine an amount of perceivable difference between a current frame and at least one previous frame and adjust a frame rate based on the determined amount of perceivable difference between the current frame and the at least one previous frame.

Abstract translation: 本公开提供了用于图像处理的系统，方法和装置。 这些系统，方法和装置可将当前帧与至少一个先前帧进行比较，以确定差异量。 可以将当前帧与至少一个先前帧之间的差异量与阈值进行比较。 另外，可以基于当前帧与至少一个先前帧和阈值之间的差的量的比较来调整帧速率。 另一示例可以确定当前帧与至少一个先前帧之间的可感知差异的量，并且基于所确定的当前帧和至少一个先前帧之间的可感知差值来调整帧速率。

公开(公告)号：US20130074085A1

公开(公告)日：2013-03-21

申请号：US13669043

申请日：2012-11-05

Applicant: Qualcomm Incorporated

Inventor： Steven S. Thomson ,  Bohuslav Rychlik ,  Ali Iranli ,  Sumit Sur ,  Norman S. Gargash

IPC: G06F1/08 ,  G06F9/46

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.

Abstract translation: 包括动态时钟和电压缩放（DCVS）解决方案，方案，系统和设备，配置为计算和实施性能保证，以确保处理器不处于忙碌状态（例如，由于临时工作负载）超过预定量 的时间高于该处理器完成其预先计算的稳态工作负载所需的时间。 DCVS可以基于可变延迟来调整处理器的频率和/或电压，以确保处理核心仅在最大程度上预定的最大工作量之下落在其稳态工作负载之后，而与工作频率或电压无关 的处理器。

公开(公告)号：US20150046685A1

公开(公告)日：2015-02-12

申请号：US14074908

申请日：2013-11-08

Applicant: QUALCOMM Incorporated

Inventor： Hee-Jun Park ,  Steven S. Thomson ,  Ronald Frank Alton ,  Edoardo Regini ,  Satish Goverdhan ,  Pieter-Louis Dam Backer

IPC: G06F9/38

CPC classification number: G06F9/38 ,  G06F1/206 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22

Abstract: The various aspects provide for a device and methods for intelligent multicore control of a plurality of processor cores of a multicore integrated circuit. The aspects may identify and activate an optimal set of processor cores to achieve the lowest level power consumption for a given workload or the highest performance for a given power budget. The optimal set of processor cores may be the number of active processor cores or a designation of specific active processor cores. When a temperature reading of the processor cores is below a threshold, a set of processor cores may be selected to provide the lowest power consumption for the given workload. When the temperature reading of the processor cores is above the threshold, a set processor cores may be selected to provide the best performance for a given power budget.

Abstract translation: 各方面提供了用于多核集成电路的多个处理器核的智能多核控制的装置和方法。 这些方面可以识别和激活一组最优化的处理器内核，以实现给定工作负载的最低级别功耗或给定功率预算的最高性能。 处理器核心的最佳集合可以是活动处理器核心的数量或特定活动处理器核心的指定。 当处理器核心的温度读数低于阈值时，可以选择一组处理器核以为给定的工作负载提供最低的功耗。 当处理器核心的温度读数高于阈值时，可以选择设置的处理器核心以为给定的功率预算提供最佳性能。

公开(公告)号：US20140181542A1

公开(公告)日：2014-06-26

申请号：US14174012

申请日：2014-02-06

Applicant: QUALCOMM Incorporated

Inventor： Sumit Sur ,  Bohuslav Rychlik ,  Steven S. Thomson ,  Ali Iranli ,  Brian J. Salsbery

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/24

Abstract: A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

Abstract translation: 公开了一种在多核中央处理单元（CPU）内控制功率的方法。 该方法可以包括监视模具温度，确定CPU的工作负载内的并行程度，以及基于平行度，模具温度或其组合来向上或向下驱动CPU的一个或多个核心。