公开(公告)号：US08952547B2

公开(公告)日：2015-02-10

申请号：US11775039

申请日：2007-07-09

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L23/485 ,  H01L27/02

CPC分类号： H01L27/088 ,  H01L21/32115 ,  H01L21/768 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/66568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.

摘要翻译： 接触结构包括形成在连接到MOS晶体管的源极/漏极区域的第一电介质层中的第一接触和形成在连接到MOS晶体管的栅极区域或第一接触点的第二介电层中的第二接触。 邻接源极/漏极区域和栅电极的对接接触结构包括形成在连接到MOS晶体管的源极/漏极区域的第一电介质层中的第一接触和形成在第二电介质层中的第二接触，其一端静止 在栅电极上，另一端与第一触点接触。

公开(公告)号：US20130258759A1

公开(公告)日：2013-10-03

申请号：US13436149

申请日：2012-03-30

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/00 ,  H01L21/66

CPC分类号： H01L27/1104 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11

摘要： An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.

公开(公告)号：US20130181297A1

公开(公告)日：2013-07-18

申请号：US13349349

申请日：2012-01-12

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/11

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1108 ,  H01L27/1211

摘要： Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction.

摘要翻译： 公开了静态随机存取存储器（SRAM）单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括上拉晶体管。 上拉晶体管包括具有半导体材料鳍的Fin场效应晶体管（FinFET）。 有源区域设置在翅片内。 触点设置在上拉晶体管的有源区上。 触点是沿第一方向设置的槽接触件。 上拉晶体管的有源区域设置在第二方向。 第二方向与第一方向非垂直。

公开(公告)号：US20120149171A1

公开(公告)日：2012-06-14

申请号：US13399488

申请日：2012-02-17

申请人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

发明人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC分类号： H01L21/762

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

摘要翻译： 公开了浅沟槽隔离（STI）结构和形成STI结构的方法。 实施例是形成半导体结构的方法。 该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。 凹部的底面通过第一材料露出，凹部的底面具有第一宽度。 加宽的凹部具有第二宽度。 第二宽度大于第一宽度。

公开(公告)号：US08059452B2

公开(公告)日：2011-11-15

申请号：US12773662

申请日：2010-05-04

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/00

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

摘要： An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.

摘要翻译： 提供集成电路和布置集成电路的方法。 集成电路包括第一和第二晶体管。 第一晶体管包括包括第一源极和第一漏极的第一有源区域; 以及在所述第一有源区上方的第一栅电极。 第二晶体管包括第二有源区，包括第二源极和第二漏极; 以及在所述第二有源区上方并连接到所述第一栅极的第二栅电极，其中所述第一源极和所述第二源极电连接，并且所述第一漏极和所述第二漏极电连接。

公开(公告)号：US20100213552A1

公开(公告)日：2010-08-26

申请号：US12773662

申请日：2010-05-04

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L29/78

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903

摘要： An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.

摘要翻译： 提供集成电路和布置集成电路的方法。 集成电路包括第一和第二晶体管。 第一晶体管包括包括第一源极和第一漏极的第一有源区域; 以及在所述第一有源区上方的第一栅电极。 第二晶体管包括第二有源区，包括第二源极和第二漏极; 以及在所述第二有源区上方并连接到所述第一栅极的第二栅电极，其中所述第一源极和所述第二源极电连接，并且所述第一漏极和所述第二漏极电连接。

公开(公告)号：US20100193877A1

公开(公告)日：2010-08-05

申请号：US12697490

申请日：2010-02-01

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/11

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.

摘要翻译： 提供具有一排捆扎单元的存储器阵列。 根据本发明的实施例，捆扎单元位于两行存储器阵列之间。 捆扎单元在列中的两个存储单元的N +有效区之间提供P +带，并在存储器阵列的列中的两个存储单元的P +有效区之间提供N +带。 带状单元在存储器阵列的两行之间提供绝缘结构，并且创建存储器单元的更均匀的操作，而不管存储器阵列内的存储器单元的位置如何。 在一个实施例中，可以沿着垂直于捆扎单元行的方向沿着存储器阵列的外边缘形成虚拟N阱。 此外，可以在捆扎单元中形成晶体管，以在带状存储单元之间提供额外的绝缘。

公开(公告)号：US07675124B2

公开(公告)日：2010-03-09

申请号：US11361248

申请日：2006-02-24

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/108 ,  H01L27/11 ,  H01L27/112

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.

公开(公告)号：US07586147B2

公开(公告)日：2009-09-08

申请号：US11405102

申请日：2006-04-17

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L21/00

CPC分类号： H01L29/41766 ,  H01L21/28531 ,  H01L21/743 ,  H01L21/7624 ,  H01L21/76802 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a source and drain region on the active region; and, a conductive contact having a first portion formed to the source region and a second portion formed through the electrical isolation region to the doped well region.

摘要翻译： 形成电连接电压节点和阱区的源极接触的对接接触结构及其形成方法，所述对接触点结构包括具有邻近半导体衬底上的电隔离区设置的阱区的有源区; MOSFET器件，其在有源区域上包括源区和漏区; 以及具有形成于所述源极区的第一部分和通过所述电隔离区形成到所述掺杂阱区的第二部分的导电接触。

公开(公告)号：US20080230855A1

公开(公告)日：2008-09-25

申请号：US11725404

申请日：2007-03-19

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L29/76

CPC分类号： H01L21/823871 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823842

摘要： A semiconductor structure with reduced inter-diffusion is provided. The semiconductor structure includes a semiconductor substrate; a first well region in the semiconductor substrate; a second well region in the semiconductor substrate; an insulating region between and adjoining the first and the second well regions; a gate dielectric layer on the first and the second well regions; and a gate electrode strip on the gate dielectric and extending from over the first well region to over the second well region. The gate electrode strip includes a first portion over the first well region, a second portion over the second well region, and a third portion over the insulating region. A thickness of the third portion is substantially less than the thicknesses of the first and the second portions.

摘要翻译： 提供具有减小的互扩散的半导体结构。 半导体结构包括半导体衬底; 半导体衬底中的第一阱区; 半导体衬底中的第二阱区; 位于第一和第二阱区之间并邻接第一和第二阱区的绝缘区; 在第一和第二阱区上的栅介质层; 以及栅极电极上的栅电极条，并从第一阱区上方延伸到第二阱区上方。 栅电极条包括第一阱区上的第一部分，第二阱区上的第二部分，以及绝缘区上的第三部分。 第三部分的厚度基本上小于第一部分和第二部分的厚度。