公开(公告)号：US20180068945A1

公开(公告)日：2018-03-08

申请号：US15796782

申请日：2017-10-28

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jean Audet ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Brian R. Sundlof

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/18 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

公开(公告)号：US09899313B2

公开(公告)日：2018-02-20

申请号：US15207077

申请日：2016-07-11

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jean Audet ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Brian R. Sundlof

IPC: H01L23/52 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19103

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

公开(公告)号：US11282773B2

公开(公告)日：2022-03-22

申请号：US16845404

申请日：2020-04-10

Applicant: International Business Machines Corporation

Inventor： Krishna R. Tunga ,  Thomas Weiss ,  Charles Leon Arvin ,  Bhupender Singh ,  Brian W. Quinlan

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/50 ,  H01L23/00 ,  H01L21/60

Abstract: An electrical device includes an electrically insulating body having an insulating body surface and a conductive pad array, a small conductive pad arranged on the insulating body surface and within the conductive pad array, and an enlarged conductive pad. The enlarged conductive pad is arranged on the insulating body and within the conductive pad array, wherein the enlarged conductive pad is spaced apart from the small conductive pad and is larger than the small conductive pad. C4 assemblies and methods of making C4 assemblies including the electrical device are also described.

公开(公告)号：US20210242139A1

公开(公告)日：2021-08-05

申请号：US16779529

申请日：2020-01-31

Applicant: International Business Machines Corporation

Inventor： Tuhin Sinha ,  Krishna R. Tunga ,  Brian W. Quinlan ,  Charles Leon Arvin ,  Steven Paul Ostrander ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/16 ,  H01L23/14 ,  H01L21/48 ,  H01L23/66 ,  H01L23/538

Abstract: A multi-chip module (MCM) package includes an organic laminate substrate; first and second semiconductor device chips that are mounted to a top side of the substrate and that define a chip gap region between opposing edges of the chips; and a stiffener that is embedded in the bottom side of the substrate. The stiffener extends across a stiffening region, which underlies the chip gap region, and does not protrude beyond a bottom side metallization of the substrate.

公开(公告)号：US20200245466A1

公开(公告)日：2020-07-30

申请号：US16851424

申请日：2020-04-17

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Jean Audet ,  Francesco Preda

IPC: H05K1/18 ,  H01G4/33 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00 ,  H05K3/30 ,  H05K1/16 ,  H05K1/02

Abstract: A device substrate includes a core material. A capacitor sheet can be affixed adjacent to a surface of the core material, where the capacitor sheet covers the surface of the core material. A first opening can extend through both capacitor sheet and the core material, where the first opening are larger than a substrate pass through-hole. An electrically inert material can fill the first opening. A second opening can extend parallel to the first opening through the electrically inert material, where the second opening is at least as large as the substrate pass through-hole and having sidewalls enclosed within the electrically inert material.

公开(公告)号：US10607928B1

公开(公告)日：2020-03-31

申请号：US16529002

申请日：2019-08-01

Applicant: International Business Machines Corporation

Inventor： Anson J. Call ,  Sushumna Iruvanti ,  Shidong Li ,  Brian W. Quinlan ,  Kamal K. Sikka ,  Rui Wang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/367 ,  H01L23/433 ,  H01L23/053 ,  H01L23/10

Abstract: An integrated circuit (IC) device carrier, such as a chip carrier, die carrier, or the like, includes a contact that locally reduces laminate strain within the IC device carrier. One type of contact pad described includes tapered sidewall(s). For example, a positively tapered contact pad includes one or more sidewalls obtusely angled relative to the contact surface of the IC carrier and a negatively tapered contact pad includes one or more sidewalls acutely angled relative to the contact surface of the IC carrier. Another type of contact pad described includes a contact pad connected to one or more pillars. The pillar(s) are also connected to a ring formed within an internal wiring level of the IC device carrier.

公开(公告)号：US10586782B2

公开(公告)日：2020-03-10

申请号：US15640475

申请日：2017-07-01

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Clement J. Fortin ,  Christopher D. Muzzy ,  Brian W. Quinlan ,  Thomas A. Wassick ,  Thomas Weiss

IPC: H01L23/00 ,  H01L23/498

Abstract: A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate.

公开(公告)号：US10566275B2

公开(公告)日：2020-02-18

申请号：US16248013

申请日：2019-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Charles L. Arvin ,  Brian M. Erwin ,  Brian W. Quinlan

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16

Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.

公开(公告)号：US10224274B2

公开(公告)日：2019-03-05

申请号：US15796782

申请日：2017-10-28

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jean Audet ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Brian R. Sundlof

IPC: H01L23/00 ,  H01L23/50 ,  H01L25/18 ,  H01L23/367 ,  H01L23/498 ,  H01L23/522

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.

公开(公告)号：US10224273B2

公开(公告)日：2019-03-05

申请号：US15796770

申请日：2017-10-28

Applicant: International Business Machines Corporation

Inventor： Charles L. Arvin ,  Jean Audet ,  Brian W. Quinlan ,  Charles L. Reynolds ,  Brian R. Sundlof

IPC: H01L23/00 ,  H01L23/50 ,  H01L25/18 ,  H01L23/367 ,  H01L23/498 ,  H01L23/522

Abstract: A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and a interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip.