公开(公告)号：US11569173B2

公开(公告)日：2023-01-31

申请号：US15857752

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Digvijay A. Raorane ,  Wilfred Gomes ,  Ravindranath V. Mahajan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L21/50 ,  H01L25/18

Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.

公开(公告)号：US11462521B2

公开(公告)日：2022-10-04

申请号：US16022677

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/64 ,  H01L23/36

Abstract: A package is disclosed. The package includes a base die. The base die includes voltage regulating circuitry and input and output (I/O) circuitry. The I/O circuitry surrounds the voltage regulating circuitry. The package also includes a top set of dies. The top set of dies includes a plurality of dies that include logic circuitry and a plurality of dies that include passive components. The plurality of dies that include passive components surround the plurality of dies that include logic circuitry. The plurality of dies that includes passive components is coupled to the logic circuitry and to the voltage regulating circuitry.

公开(公告)号：US11322445B2

公开(公告)日：2022-05-03

申请号：US16319647

申请日：2016-09-12

Applicant: Intel Corporation

Inventor： Yidnekachew S. Mekonnen ,  Dae-Woo Kim ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/34 ,  H01L23/48 ,  H01L21/44 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Embedded Multi-die Interconnect Bridge (EMIB) technology provides a bridge die, where the EMIB includes multiple signal and power routing layers. The EMIB eliminates the need for TSVs required by the SIP assembly silicon interposers. In an embodiment, the EMIB includes at least one copper pad. The copper pad may be configured to protect the EMIB during wafer thinning. The copper pad may be connected to another copper pad to provide signal routing, thereby increasing the signal contact density. The copper pad may be configured to provide an increased power delivery to one or more connected dies.

公开(公告)号：US11276635B2

公开(公告)日：2022-03-15

申请号：US16636620

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sujit Sharan ,  Kemal Aygun ,  Zhiguo Qian ,  Yidnekachew Mekonnen ,  Zhichao Zhang ,  Jianyong Xie

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US11257743B2

公开(公告)日：2022-02-22

申请号：US16542248

申请日：2019-08-15

Applicant: Intel Corporation

Inventor： Arnab Sarkar ,  Sujit Sharan ,  Dae-Woo Kim

IPC: H01L23/498 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

公开(公告)号：US11195805B2

公开(公告)日：2021-12-07

申请号：US15942092

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Sujit Sharan ,  Jianyong Xie

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L25/00 ,  H01L21/48 ,  H01L25/16 ,  H01L23/48

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US11031288B2

公开(公告)日：2021-06-08

申请号：US16252420

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Sujit Sharan ,  Ravindranath Mahajan ,  Stefan Rusu ,  Donald S. Gardner

IPC: H01L21/78 ,  H01L23/48 ,  H01L23/522 ,  H01L25/16 ,  H01L49/02 ,  H01L23/538

Abstract: Integrated passive components in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die including a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

公开(公告)号：US20190096798A1

公开(公告)日：2019-03-28

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/50 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/40 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

公开(公告)号：US10236209B2

公开(公告)日：2019-03-19

申请号：US14583015

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sujit Sharan ,  Ravindranath Mahajan ,  Stefan Rusu ,  Donald S. Gardner

IPC: H01L21/78 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02 ,  H01L23/538 ,  H01L23/522 ,  H01L27/08

Abstract: Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

公开(公告)号：US10177083B2

公开(公告)日：2019-01-08

申请号：US15749462

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Sujit Sharan

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/00 ,  H01L23/48

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.