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    Method for stacking core and uncore dies having landing slots
    1.
    发明授权
    Method for stacking core and uncore dies having landing slots 有权

    公开(公告)号：US10431573B2

    公开(公告)日：2019-10-01

    申请号：US15370904

    申请日：2016-12-06

    Applicant: Intel Corporation

    Inventor： Stefan Rusu

    IPC: H01L25/065 ,  H01L25/00 ,  H01L25/18 ,  G06F15/76 ,  H01L23/48 ,  H01L23/544 ,  G06F12/1045

    Abstract: A method is described for stacking a plurality of cores. For example, one embodiment comprises: mounting an uncore die on a package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die; and vertically coupling a first cores die comprising a first plurality of cores on top of the uncore die, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die.

    METHOD AND APPARATUS FOR STACKING A PLURALITY OF CORES
    4.
    发明申请
    METHOD AND APPARATUS FOR STACKING A PLURALITY OF CORES 有权
    堆叠多孔的方法和装置

    公开(公告)号：US20160092396A1

    公开(公告)日：2016-03-31

    申请号：US14498353

    申请日：2014-09-26

    Applicant: INTEL CORPORATION

    Inventor： Stefan Rusu

    IPC: G06F15/76 ,  H05K3/00 ,  H05K1/18 ,  H05K3/30

    CPC classification number: H01L25/18 ,  G06F12/1045 ,  G06F15/76 ,  G06F2212/1008 ,  G06F2212/283 ,  G06F2212/455 ,  G06F2212/608 ,  G06F2212/68 ,  H01L23/481 ,  H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus and method are described for stacking a plurality of cores. For example, one embodiment of an apparatus comprises: a package; an uncore die mounted on the package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus; and a first cores die comprising a first plurality of cores, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.

    Abstract translation: 描述了用于堆叠多个核的装置和方法。 例如，装置的一个实施例包括：包装; 安装在所述封装上的非芯模，所述裸芯包括多个暴露的着陆槽，每个着陆槽包括可垂直地连接到芯模的管芯间界面，所述裸芯包括多个可由核心内部的芯部 核心包括存储器控制器组件，级别3（L3）高速缓存，系统存储器或系统存储器接口以及核心互连结构或总线; 以及包括第一多个芯的第一芯芯，所述芯在所述第一芯上分开，以对应于所述裸芯上的所述着陆槽的全部或第一子集，所述芯中的每一个具有定位成为 当所述第一芯管芯垂直耦合在所述裸芯管的顶部上时，在所述非芯管芯上的着陆槽内通信地耦合到相应的晶片间界面，其中芯体的晶片间界面与晶片间的交流耦合 其对应的着陆槽的接口将核心通信地耦合到裸芯片的非零部件。

    APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT
    6.
    发明申请
    APPARATUS AND METHOD FOR REDUCING LEAKAGE POWER OF A CIRCUIT 审中-公开
    降低电路泄漏功率的装置和方法

    公开(公告)号：US20160077567A1

    公开(公告)日：2016-03-17

    申请号：US14948174

    申请日：2015-11-20

    Applicant: Intel Corporation

    Inventor： Gururaj K. Shamanna ,  Stefan Rusu ,  Phani Kumar Kandula ,  Sankalan Prasad ,  Mandar R. Ranade ,  Narayanan Natarajan ,  Tessil Thomas

    IPC: G06F1/28 ,  G05F1/625

    CPC classification number: G06F1/28 ,  G05F1/625 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

    Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

    Abstract translation: 描述了一种处理器，包括：多个晶体管，其可操作以提供动态可调节的晶体管尺寸，所述多个晶体管的一端耦合到第一电源并在另一端耦合到第二电源; 耦合到所述第二电源的电路，所述第二电源向所述电路提供电力; 以及功率控制单元（PCU），用于监测第一电源的电平，并且动态地调整多个晶体管的晶体管尺寸，使得调节第二电源以保持电路的可操作性。

    Integrated clock differential buffering
    7.
    发明授权
    Integrated clock differential buffering 有权
    集成时钟差分缓冲

    公开(公告)号：US08860479B2

    公开(公告)日：2014-10-14

    申请号：US13929164

    申请日：2013-06-27

    Applicant: Intel Corporation

    Inventor： Choupin Huang ,  Vijaya K. Boddu ,  Stefan Rusu ,  Nicholas B Peterson

    IPC: H03L7/06 ,  H03L7/07 ,  H03L7/089 ,  H03L7/08

    CPC classification number: H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

    Abstract: Integrated clock differential buffering. A first phase locked loop (PLL) circuit having a first clocking ratio is coupled to receive an input differential clock signal. The first PLL circuit generates a first reference clock signal. A second PLL circuit having a second clocking ratio is coupled to receive the input differential clock signal. The second PLL circuit to generate a second reference clock signal. A first set of clock signal output buffers are coupled to receive the first reference clock signal and to provide a first differential reference clock signal corresponding to the first reference clock signal. A second set of clock signal output buffers is coupled to receive the second reference clock signal and to provide a second differential reference clock signal corresponding to the second reference clock signal. The first PLL circuit, the second PLL circuit, the first set of output buffers and the second set of output buffers reside within an integrated circuit package also having a die to receive at least the first differential reference clock signal.

    Abstract translation: 集成时钟差分缓冲。 具有第一时钟比率的第一锁相环（PLL）电路被耦合以接收输入差分时钟信号。 第一PLL电路产生第一参考时钟信号。 具有第二时钟比的第二PLL电路被耦合以接收输入差分时钟信号。 第二个PLL电路产生第二个参考时钟信号。 耦合第一组时钟信号输出缓冲器以接收第一参考时钟信号并提供对应于第一参考时钟信号的第一差分参考时钟信号。 第二组时钟信号输出缓冲器被耦合以接收第二参考时钟信号并提供对应于第二参考时钟信号的第二差分参考时钟信号。 第一PLL电路，第二PLL电路，第一组输出缓冲器和第二组输出缓冲器驻留在还具有至少接收第一差分参考时钟信号的管芯的集成电路封装中。

    Method and machine-readable medium for configuring processors with base dies having landing slots
    8.
    发明授权
    Method and machine-readable medium for configuring processors with base dies having landing slots 有权

    公开(公告)号：US10923463B2

    公开(公告)日：2021-02-16

    申请号：US16590057

    申请日：2019-10-01

    Applicant: Intel Corporation

    Inventor： Stefan Rusu

    IPC: G06F15/76 ,  H01L25/18 ,  H01L25/065 ,  H01L23/48 ,  H01L23/544 ,  H01L25/00 ,  G06F12/1045

    Abstract: A method is described for configuring a custom server processor including a base die and related components. For example, one embodiment includes: providing a secure website to a user for configuring a custom server processor, the secure website including a graphical user interface (GUI); providing a first graphical element from which a user is to select a base die and an associated package; providing a second graphical element including a plurality of building block options selectable by the user to populate landing slots in the selected base die; providing a third graphical element including a visual representation of a user configuration that includes one or more building blocks selected by the user in the second graphical element and arranged on the base die selected by the user in the first graphical element; and performing a verification of the user configuration.

    Apparatus, method, and system for adaptive compensation of reverse temperature dependence
    10.
    发明授权
    Apparatus, method, and system for adaptive compensation of reverse temperature dependence 有权

    公开(公告)号：US10013045B2

    公开(公告)日：2018-07-03

    申请号：US15144332

    申请日：2016-05-02

    Applicant: INTEL CORPORATION

    Inventor： Stefan Rusu

    IPC: G06F1/32 ,  G06F11/30 ,  G06F1/20

    CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  Y02D10/126 ,  Y02D10/16

    Abstract: Described herein are an apparatus, method, and system for adaptive compensation for reverse temperature dependence in a processor. The apparatus comprises: a first sensor to determine operating temperature of a processor; a second sensor to determine behavior of the processor; and a control unit to determine a frequency of a clock signal for the processor and a power supply level for the processor according to the determined operating temperature and behavior of the processor, wherein the control unit to increase the power supply level from an existing power supply level, and/or reduce frequency of the clock signal from an existing frequency of the clock signal when the operating temperature is in a region of reverse temperature dependence (RTD).

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