公开(公告)号：US10665715B2

公开(公告)日：2020-05-26

申请号：US16114613

申请日：2018-08-28

Applicant: International Business Machines Corporation

Inventor： Praveen Joseph ,  Indira Seshadri ,  Ekmini A. De Silva ,  Stuart A. Sieg

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.

公开(公告)号：US20200098639A1

公开(公告)日：2020-03-26

申请号：US16139932

申请日：2018-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Indira Seshadri ,  Stuart A. Sieg ,  Praveen Joseph ,  Ekmini A. De Silva

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311

Abstract: A method of preventing the collapse of fin structures is provided. The method includes forming a plurality of vertical fins on a substrate, and a hard mask stack on each of the vertical fins. The method further includes forming a cover layer on the plurality of vertical fins and hard mask stacks, and reducing the height of the cover layer to expose an upper portion of each of the hard mask stacks. The method further includes forming a bracing layer on the reduced height cover layer and exposed portion of each of the hard mask stacks, and removing a portion of the bracing layer to expose a portion of the reduced height cover layer and form a bracing segment on the exposed portion of each of the hard mask stacks. The method further includes removing the reduced height cover layer.

公开(公告)号：US10535529B2

公开(公告)日：2020-01-14

申请号：US16000485

申请日：2018-06-05

Applicant: International Business Machines Corporation

Inventor： Praveen Joseph ,  Ekmini A. De Silva ,  Stuart A. Sieg ,  Eric Miller

IPC: H01L29/80 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

公开(公告)号：US10461172B2

公开(公告)日：2019-10-29

申请号：US15850585

申请日：2017-12-21

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Hemanth Jagannathan ,  Yann Mignot ,  Stuart A. Sieg

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/40 ,  H01L21/311

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device by forming a channel fin over a substrate, wherein the channel fin includes a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing. An initial gate structure is formed over the plurality of channels. Formed along sidewalls of the initial gate structure are spacers that each has a predetermined spacer height, wherein a thickness of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing. Portions of the initial gate structure that are not covered by the spacers are removed.

公开(公告)号：US20190318935A1

公开(公告)日：2019-10-17

申请号：US15950628

申请日：2018-04-11

Applicant: International Business Machines Corporation

Inventor： Romain Lallement ,  Stuart A. Sieg

IPC: H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L21/66 ,  G06F17/50

Abstract: A method for modeling planarization performance of a given material includes patterning a first photoresist layer over a first material deposited over a substrate. The method also includes etching portions of the first material exposed by the patterned first photoresist layer to create a patterned topography of the first material comprising two or more different design macros in two or more different regions. The method further includes coating the given material over the patterned topography of the first material, patterning a second photoresist layer over the given material, measuring the critical dimension of a metrology feature in each of the two or more different regions, and utilizing the measured critical dimensions of the metrology feature in the two or more different regions to generate a model of the planarization performance of the given material by relating the measured critical dimensions to focal planes of the given material.

公开(公告)号：US10304744B1

公开(公告)日：2019-05-28

申请号：US15980427

申请日：2018-05-15

Applicant: International Business Machines Corporation

Inventor： Praveen Joseph ,  Ekmini Anuja De Silva ,  Fee Li Lie ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L21/033

Abstract: Various methods and structures for fabricating a plurality of vertical fins in a vertical fin pattern on a semiconductor substrate where the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. Adjacent vertical fins in the vertical fin pattern can be all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance.

公开(公告)号：US10121853B2

公开(公告)日：2018-11-06

申请号：US15794636

申请日：2017-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

公开(公告)号：US20180269060A1

公开(公告)日：2018-09-20

申请号：US15463659

申请日：2017-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John C. Arnold ,  Anuja E. DeSilva ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A.M. Mignot ,  Stuart A. Sieg

IPC: H01L21/033

Abstract: Methods of forming fins include forming mask fins on a protection layer over a seed layer. Seed layer fins are etched out of the seed layer. Self-assembled fins are formed by directed self-assembly on the seed layer fins. A three-color hardmask fin pattern that has hardmask fins of three mutually selectively etchable compositions is formed using the self-assembled fins as a mask. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

公开(公告)号：US20180247825A1

公开(公告)日：2018-08-30

申请号：US15802634

申请日：2017-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sean D. Burns ,  Nelson M. Felix ,  Chi-Chun Liu ,  Yann A.M. Mignot ,  Stuart A. Sieg

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

公开(公告)号：US10032680B2

公开(公告)日：2018-07-24

申请号：US14984215

申请日：2015-12-30

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.