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    Semiconductor devices having different gate oxide thicknesses
    31.
    发明授权
    Semiconductor devices having different gate oxide thicknesses 有权
    具有不同栅极氧化物厚度的半导体器件

    公开(公告)号：US09087722B2

    公开(公告)日：2015-07-21

    申请号：US14541182

    申请日：2014-11-14

    Applicant: International Business Machines Corporation

    Inventor： Charlotte D. Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

    IPC: H01L29/02 ,  H01L27/088 ,  H01L29/423

    CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

    Abstract translation: 制造具有不同厚度栅极氧化物的多个finFET器件的方法。 该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部 氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

    Structure and method of Tinv scaling for high k metal gate technology
    32.
    发明授权
    Structure and method of Tinv scaling for high k metal gate technology 有权
    用于高k金属栅极技术的Tinv缩放的结构和方法

    公开(公告)号：US09006837B2

    公开(公告)日：2015-04-14

    申请号：US13793682

    申请日：2013-03-11

    Applicant: International Business Machines Corporation

    Inventor： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

    IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238

    CPC classification number: H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

    Abstract: A complementary metal oxide semiconductor structure including a scaled 0 and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and a pFET threshold voltage adjusted species.

    Abstract translation: 提供了包括缩放的0和在操作期间不表现出增加的阈值电压和降低的移动性的定标pFET的互补金属氧化物半导体结构。 该方法包括在nFET栅极堆叠内形成等离子体氮化nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以是等离子体氮化的。 等离子体氮化，nFET阈值电压调节的高k栅极电介质层部分包含高达15原子％的N 2和nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分含有高达15原子％ N2和pFET阈值电压调整种。

    Concurrently Forming nFET and pFET Gate Dielectric Layers
    33.
    发明申请
    Concurrently Forming nFET and pFET Gate Dielectric Layers 有权
    并联形成nFET和pFET栅介质层

    公开(公告)号：US20140187028A1

    公开(公告)日：2014-07-03

    申请号：US13732455

    申请日：2013-01-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Yanfeng Wang ,  Jinping Liu

    IPC: H01L21/8238

    CPC classification number: H01L21/823857

    Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

    ETCH STOP LAYER FORMATION IN METAL GATE PROCESS
    34.
    发明申请
    ETCH STOP LAYER FORMATION IN METAL GATE PROCESS 审中-公开
    金属浇口过程中的阻止层形成

    公开(公告)号：US20130277767A1

    公开(公告)日：2013-10-24

    申请号：US13780957

    申请日：2013-02-28

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Zhengwen Li ,  Michael P. Chudzik ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Richard S. Wise

    IPC: H01L29/51

    CPC classification number: H01L29/517 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/0228 ,  H01L21/31116 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/66545

    Abstract: A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

    Abstract translation: 一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构的金属栅极导体。 栅极电介质盖形成在金属栅极导体上。 栅极电介质盖是由栅极导体的金属元件催化的氧化硅，使得栅极电介质盖的边缘与金属栅极导体的侧壁对准。 接触件然后形成在栅极结构的相对侧上的源极区域和漏极区域中的至少一个，其中栅极电介质盖阻挡触点与金属栅极导体接触。

    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT
    35.
    发明申请
    REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT 有权
    具有降低闸门泄漏电流的更换门

    公开(公告)号：US20130217219A1

    公开(公告)日：2013-08-22

    申请号：US13842217

    申请日：2013-03-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

    IPC: H01L21/28

    CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

    Abstract: Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

    Abstract translation: 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

    STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY
    36.
    发明申请
    STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY 审中-公开
    高k金属门技术的镀层结构与方法

    公开(公告)号：US20130187239A1

    公开(公告)日：2013-07-25

    申请号：US13793682

    申请日：2013-03-11

    Applicant: International Business Machines Corporation

    Inventor： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

    IPC: H01L27/092

    CPC classification number: H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

    Abstract: A complementary metal oxide semiconductor structure including a scaled nFET and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % N2 and a pFET threshold voltage adjusted species.

    Abstract translation: 提供了包括缩放的nFET和定标pFET的互补金属氧化物半导体结构，其在操作期间不表现出增加的阈值电压和降低的迁移率。 该方法包括在nFET栅极堆叠内形成等离子体氮化nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以是等离子体氮化的。 等离子体氮化，nFET阈值电压调节的高k栅极电介质层部分包含高达15原子％的N 2和nFET阈值电压调节的物质，而等离子体氮化pFET阈值电压调节的高k栅介质层部分含有高达15原子％ N2和pFET阈值电压调整种。

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