知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

103 records (took 0.019 seconds)

    Concurrently Forming nFET and pFET Gate Dielectric Layers
    1.
    发明申请
    Concurrently Forming nFET and pFET Gate Dielectric Layers 有权
    并联形成nFET和pFET栅介质层

    公开(公告)号：US20140187028A1

    公开(公告)日：2014-07-03

    申请号：US13732455

    申请日：2013-01-02

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Yanfeng Wang ,  Jinping Liu

    IPC: H01L21/8238

    CPC classification number: H01L21/823857

    Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER
    2.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER 有权
    制造半导体器件的方法，包括更换金属栅极工艺，包括导电的DUMMY GATE层

    公开(公告)号：US20140120708A1

    公开(公告)日：2014-05-01

    申请号：US13664744

    申请日：2012-10-31

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

    IPC: H01L21/28

    CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

    Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

    Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

    Concurrently forming nFET and pFET gate dielectric layers
    3.
    发明授权
    Concurrently forming nFET and pFET gate dielectric layers 有权
    同时形成nFET和pFET栅极电介质层

    公开(公告)号：US09059315B2

    公开(公告)日：2015-06-16

    申请号：US13732455

    申请日：2013-01-02

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, Jr. ,  Yanfeng Wang ,  Jinping Liu

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

    CPC classification number: H01L21/823857

    Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    Abstract translation: 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域之上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

    Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer
    4.
    发明授权
    Method of manufacturing semiconductor devices including replacement metal gate process incorporating a conductive dummy gate layer 有权
    包括具有导电虚拟栅极层的替代金属栅极工艺的半导体器件的制造方法

    公开(公告)号：US08835292B2

    公开(公告)日：2014-09-16

    申请号：US13664744

    申请日：2012-10-31

    Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

    Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

    IPC: H01L21/3205

    CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

    Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

    Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

    Self-aligned multiple patterning processes with layered mandrels
    8.
    发明授权
    Self-aligned multiple patterning processes with layered mandrels 有权

    公开(公告)号：US10446395B1

    公开(公告)日：2019-10-15

    申请号：US15950364

    申请日：2018-04-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jiehui Shu ,  Xiaohan Wang ,  Qiang Fang ,  Zhiguo Sun ,  Jinping Liu ,  Hui Zang

    IPC: H01L21/033 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

Patent Agency Ranking