公开(公告)号：US06611052B2

公开(公告)日：2003-08-26

申请号：US10042560

申请日：2001-11-16

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

IPC: H01L2302

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07811 ,  H01L2924/00

Abstract: A stackable semiconductor package includes a semiconductor die, and has a chip sized peripheral outline matching that of the die. In addition to the die, the package includes stacking pads and stacking contacts on opposing sides of the die, and conductive grooves on the edges of the die in electrical communication with the stacking pads and the stacking contacts. The conductive grooves function as interlevel conductors for the package and can also function as edge contacts for the package. The configuration of the stacking pads, of the stacking contacts and of the conductive grooves permit multiple packages to be stacked and electrically interconnected to form stacked assemblies. A method for fabricating the package is if performed at the wafer level on a substrate, such as a semiconductor wafer, containing multiple dice. In addition, multiple substrates can be stacked, bonded and singulated to form stacked assemblies that include multiple stacked packages.

Abstract translation: 可堆叠的半导体封装包括半导体管芯，并且具有与管芯相匹配的芯片尺寸的外围轮廓。 除了管芯之外，封装还包括在管芯的相对侧上的堆叠焊盘和堆叠触点，以及与堆叠焊盘和堆叠触点电连通的管芯边缘上的导电槽。 导电槽用作封装的层间导体，并且还可以用作封装的边缘触点。 堆叠焊盘，堆叠触点和导电沟槽的配置允许多个封装堆叠并电互连以形成堆叠的组件。 如果在诸如包含多个骰子的半导体晶片的衬底上的晶片级执行封装的制造方法。 此外，可以堆叠，粘合和分割多个基板以形成包括多个堆叠封装的堆叠组件。

公开(公告)号：US20110215453A1

公开(公告)日：2011-09-08

申请号：US13110060

申请日：2011-05-18

Applicant: Meow Koon Eng ,  Chia Yong Poo ,  Boon Suan Jeung ,  Tay Wuu Yean

Inventor： Meow Koon Eng ,  Chia Yong Poo ,  Boon Suan Jeung ,  Tay Wuu Yean

IPC: H01L25/11

CPC classification number: H01L23/49527 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/01078

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

Abstract translation: 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，一种制造微电子器件的方法包括将具有第一介电壳体的第一管芯封装堆叠在具有第二介电壳体的第二管芯封装的顶部上，使第一壳体的侧表面上的第一金属引线与第二金属 在第二壳体的第二侧表面处引导，并且形成将单独的第一引线连接到单独的第二引线的金属焊料连接器。 在另一个实施例中，制造微电子器件的方法还可以包括通过将金属焊料施加到第一侧表面的一部分，第二侧表面的一部分，以及跨越第一管芯封装和第二侧表面之间的间隙来形成连接器 第二管芯封装，使得连接器由金属焊料形成，其润湿到各个第一引线和各个第二引线。

公开(公告)号：US20110175206A1

公开(公告)日：2011-07-21

申请号：US13074938

申请日：2011-03-29

Applicant: Chua Swee Kwang ,  Boon Suan Jeung ,  Chia Yong Poo

Inventor： Chua Swee Kwang ,  Boon Suan Jeung ,  Chia Yong Poo

IPC: H01L29/41 ,  H01L29/06

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/24227 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/4899 ,  H01L2224/4943 ,  H01L2224/76155 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/85045 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00

Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.

Abstract translation: 本文公开了包括用于形成这种互连的互连和方法的半导体器件和组件。 制造半导体器件的方法的一个实施例包括在具有排成行和列的多个管芯的模制晶片的模制部分中形成多个第一侧沟槽至中间深度。 该方法还包括在与第一侧沟槽对准的区域处从模制部分的第二侧移除材料，其中去除材料通过模制部分形成开口。 该方法还包括在开口处在模制部分的第二侧处形成多个电触头，并将第二侧触点电连接到模具上相应的键合位置。

公开(公告)号：US20100133662A1

公开(公告)日：2010-06-03

申请号：US12696182

申请日：2010-01-29

Applicant: Chua Swee Kwang ,  Boon Suan Jeung ,  Chia Yong Poo

Inventor： Chua Swee Kwang ,  Boon Suan Jeung ,  Chia Yong Poo

IPC: H01L23/522

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/24227 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/4899 ,  H01L2224/4943 ,  H01L2224/76155 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/85045 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00

Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.

Abstract translation: 本文公开了包括用于形成这种互连的互连和方法的半导体器件和组件。 制造半导体器件的方法的一个实施例包括在具有排成行和列的多个管芯的模制晶片的模制部分中形成多个第一侧沟槽至中间深度。 该方法还包括在与第一侧沟槽对准的区域处从模制部分的第二侧移除材料，其中去除材料通过模制部分形成开口。 该方法还包括在开口处在模制部分的第二侧处形成多个电触头，并将第二侧触点电连接到模具上相应的键合位置。

公开(公告)号：US07226809B2

公开(公告)日：2007-06-05

申请号：US10440590

申请日：2003-05-19

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

IPC: H01L21/44

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Abstract translation: 多芯片组件包括在其外围边缘上具有外部连接器的半导体器件或半导体器件部件。 外部连接器通过沿相邻的未切割半导体器件或半导体器件部件之间的边界线形成通孔而形成，然后用导电材料电镀或填充孔。 当相邻的半导体器件或半导体器件部件彼此切断时，半导体器件之间的每个通孔中的导电材料被二等分。 多芯片组件的半导体器件和组件可以具有不同的尺寸，以及具有不同直径和间距的外部连接器阵列。 每个外部连接器的一端或两端可以电连接到另一个对准的外部连接器或另一个半导体器件或组件的接触区域。 以这种方式组装提供了低调的堆叠组件。

公开(公告)号：US06818977B2

公开(公告)日：2004-11-16

申请号：US10197986

申请日：2002-07-17

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

IPC: H01L2302

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Abstract translation: 多芯片组件包括在其外围边缘上具有外部连接器的半导体器件或半导体器件部件。 外部连接器通过沿相邻的未切割半导体器件或半导体器件部件之间的边界线形成通孔而形成，然后用导电材料电镀或填充孔。 当相邻的半导体器件或半导体器件部件彼此切断时，半导体器件之间的每个通孔中的导电材料被二等分。 多芯片组件的半导体器件和组件可以具有不同的尺寸，以及具有不同直径和间距的外部连接器阵列。 每个外部连接器的一端或两端可以电连接到另一个对准的外部连接器或另一个半导体器件或组件的接触区域。 以这种方式组装提供了低调的堆叠组件。

公开(公告)号：US06841418B2

公开(公告)日：2005-01-11

申请号：US10767290

申请日：2004-01-28

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

IPC: H01L21/60 ,  H01L23/31 ,  H01L25/065 ,  H01L21/44

CPC classification number: H01L23/3114 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A microelectronic package and method for manufacture. The package can include first and second microelectronic substrates, each having a first surface with a connection site, and a second surface facing opposite the first surface. The second microelectronic substrate can be coupled to the first microelectronic substrate with the second surface of the second microelectronic substrate facing towards the first surface of the first microelectronic substrate. A conformal conductive link formed, for example, from sequentially deposited portions of conductive material, can be coupled between the first and second connection sites to provide for electrical communication between the substrates. Accordingly, the substrates can be stacked and electrically connected to reduce the footprint occupied by the substrates.

Abstract translation: 一种微电子封装及其制造方法。 封装可以包括第一和第二微电子基板，每个具有连接部位的第一表面和与第一表面相对的第二表面。 第二微电子衬底可以耦合到第一微电子衬底，第二微电子衬底的第二表面面向第一微电子衬底的第一表面。 例如由顺序沉积的导电材料部分形成的保形导电连接可连接在第一和第二连接部位之间，以提供基板之间的电连通。 因此，可以堆叠和电连接基板以减少由基板占据的占地面积。

公开(公告)号：US06743696B2

公开(公告)日：2004-06-01

申请号：US10285148

申请日：2002-10-30

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf

IPC: H01L2130

CPC classification number: H01L25/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48472 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/85399 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/07025 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

公开(公告)号：US06727116B2

公开(公告)日：2004-04-27

申请号：US10183820

申请日：2002-06-27

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo ,  Chua Swee Kwang

IPC: H01L2144

CPC classification number: H01L23/49838 ,  H01L23/49805 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/00

Abstract: A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.

Abstract translation: 公开了一种相对于X，Y和Z轴中的每一个基本上模具尺寸的半导体器件封装。 该包装件包括沿其至少一个周边边缘定位的外部连接器，并且基本上横跨周边边缘的高度延伸。 每个外部连接器通过在位于与封装的半导体器件的外周相邻的街道处切断基本上穿过基板坯料（例如硅晶片）的导电通孔来形成。 外部连接器可以包括至少部分地接收从支撑基板突出的导电柱的凹部。 组件可以包括堆叠布置的封装，而不增加高度的连接器。

公开(公告)号：US20090057843A1

公开(公告)日：2009-03-05

申请号：US11933754

申请日：2007-11-01

Applicant: Chua Swee Kwang ,  Boon Suan Jeung ,  Chia Yong Poo

Inventor： Chua Swee Kwang ,  Boon Suan Jeung ,  Chia Yong Poo

IPC: H01L23/49 ,  H01L21/304 ,  H01L21/60

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/24227 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/4899 ,  H01L2224/4943 ,  H01L2224/76155 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/85045 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00

Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.

Abstract translation: 本文公开了包括用于形成这种互连的互连和方法的半导体器件和组件。 制造半导体器件的方法的一个实施例包括在具有排成行和列的多个管芯的模制晶片的模制部分中形成多个第一侧沟槽至中间深度。 该方法还包括在与第一侧沟槽对准的区域处从模制部分的第二侧移除材料，其中去除材料通过模制部分形成开口。 该方法还包括在开口处在模制部分的第二侧处形成多个电触头，并将第二侧触点电连接到模具上相应的键合位置。