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31.发明授权Thin film transistor and manufacturing method thereof, an array substrate and a display device 有权薄膜晶体管及其制造方法，阵列基板和显示装置公开(公告)号：US09502570B2
公开(公告)日：2016-11-22
申请号：US14057728
申请日：2013-10-18
Applicant: BOE Technology Group Co., Ltd.
IPC: H01L21/28 , H01L29/786 , H01L29/423 , H01L29/49 , H01L27/12 , H01L29/66
CPC classification number: H01L29/786 , H01L21/28008 , H01L27/124 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/7869
Abstract: Embodiments of the present invention provide a thin film transistor and its manufacturing method, an array substrate and a display device, to improve the electrical performance of the thin film transistor and improve the picture quality of images displayed by the display device. The thin film transistor includes: a substrate; a gate, a source, a drain and a semiconductor layer formed on the substrate; a first gate protection layer; a gate isolation layer; and a second gate protection layer. The first gate protection layer is at least partly located between the gate and the semiconductor layer, and is an insulating layer. The gate isolation layer is at least partly located between the first gate protection layer and the second gate protection layer, and is a conductive layer. The second gate protection layer is at least partly located between the gate isolation layer and the semiconductor layer, and is an insulating layer.
Abstract translation: 本发明的实施例提供薄膜晶体管及其制造方法，阵列基板和显示装置，以改善薄膜晶体管的电性能并提高由显示装置显示的图像的图像质量。 薄膜晶体管包括：基板; 形成在基板上的栅极，源极，漏极和半导体层; 第一栅极保护层; 栅极隔离层; 和第二栅极保护层。 第一栅极保护层至少部分地位于栅极和半导体层之间，并且是绝缘层。 栅极隔离层至少部分地位于第一栅极保护层和第二栅极保护层之间，并且是导电层。 第二栅极保护层至少部分地位于栅极隔离层和半导体层之间，并且是绝缘层。
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32.发明授权Thin-film transistor (TFT), manufacturing method thereof, array substrate, display device and barrier layer 有权薄膜晶体管（TFT），其制造方法，阵列基板，显示装置和阻挡层公开(公告)号：US09331165B2
公开(公告)日：2016-05-03
申请号：US14127858
申请日：2013-10-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
CPC classification number: H01L29/4966 , H01L27/1225 , H01L27/124 , H01L27/1259 , H01L29/45 , H01L29/495 , H01L29/66969 , H01L29/78606 , H01L29/7869
Abstract: The present invention discloses a thin-film transistor (TFT), a manufacturing method thereof, an array substrate and a display device. The present invention is used for improving the electrical properties of the TFT and the image quality of the display device. The TFT provided by the present invention comprises: a gate electrode, a source electrode, a drain electrode, a semiconductor layer, a gate electrode insulating layer and a first metal barrier layer, which are disposed on a substrate; the gate electrode insulating layer is disposed between the gate electrode and the semiconductor layer; and the first metal barrier layer is disposed between the source/drain electrodes and the gate electrode insulating layer, and the first metal barrier layer is arranged on the same layer as the semiconductor layer and configured to prevent interdiffusion between the material for forming the source/drain electrodes and the material for forming the gate electrode.
Abstract translation: 本发明公开了一种薄膜晶体管（TFT），其制造方法，阵列基板和显示装置。 本发明用于改善TFT的电性能和显示装置的图像质量。 本发明提供的TFT包括：设置在基板上的栅电极，源电极，漏电极，半导体层，栅电极绝缘层和第一金属阻挡层; 栅电极绝缘层设置在栅电极和半导体层之间; 并且第一金属阻挡层设置在源/漏电极和栅电极绝缘层之间，并且第一金属阻挡层设置在与半导体层相同的层上，并且被配置为防止用于形成源/漏电极的材料之间的相互扩散， 漏电极和用于形成栅电极的材料。
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公开(公告)号：US09054195B2
公开(公告)日：2015-06-09
申请号：US14079134
申请日：2013-11-13
Applicant: Boe Technology Group Co., Ltd.
IPC: H01L29/10 , H01L21/00 , H01L29/786 , H01L29/66
CPC classification number: H01L29/786 , H01L27/1218 , H01L27/1225 , H01L27/1262 , H01L29/66742
Abstract: Embodiments of the present application provide an array substrate and a method for fabricating the same. The array substrate comprises: a base substrate, a plurality of thin film transistors formed on the base substrate; the array substrate also comprising: a buffer layer formed on the substrate between the substrate and the film transistors; wherein, the buffer layer is a metal oxide film layer. Embodiments of the present application also provide a display device having such array substrate.
Abstract translation: 本申请的实施例提供阵列基板及其制造方法。 阵列基板包括：基底基板，形成在基底基板上的多个薄膜晶体管; 所述阵列基板还包括：形成在所述基板上的所述基板和所述薄膜晶体管之间的缓冲层; 其中，缓冲层是金属氧化物膜层。 本申请的实施例还提供了具有这种阵列基板的显示装置。
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公开(公告)号：US20140061635A1
公开(公告)日：2014-03-06
申请号：US13995932
申请日：2012-11-23
Applicant: BOE Technology Group Co., Ltd.
Inventor： Xiang Liu
IPC: H01L27/12
CPC classification number: H01L27/127 , G02F1/1368 , G02F2001/136231 , G02F2001/136295 , H01L27/1214 , H01L27/1288 , H01L29/66765
Abstract: An array substrate, a manufacturing method thereof and a display device are provided. In the manufacturing method, the needed patterns can be formed by just three photolithography processes, wherein the semiconductor layer and the etch stop layer are formed by just one photolithography process. The method reduces one photolithography process compared to the method of the state of the art, which forms the pattern of the semiconductor layer and the etch stop layer by two photolithography processes respectively, thereby greatly reducing the manufacturing cost and improving the production efficiency.
Abstract translation: 提供阵列基板，其制造方法和显示装置。 在制造方法中，所需的图案可以仅通过三个光刻工艺形成，其中半导体层和蚀刻停止层仅通过一个光刻工艺形成。 与现有技术的方法相比，该方法减少了一个光刻工艺，其分别通过两个光刻工艺形成半导体层和蚀刻停止层的图案，从而大大降低了制造成本并提高了生产效率。
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公开(公告)号：US20200071814A1
公开(公告)日：2020-03-05
申请号：US16396734
申请日：2019-04-28
Inventor： Jinbiao Liu , Luoyang Feng , Youliang Li , Tianyu Xu , Rui Tan , Yongyong Wei , Xiang Liu , Li Chen , Kai Wen , Qinwen Jiang , Shangshu Sun , Peng Liu
Abstract: An evaporation source includes a crucible and a heater for generating heat radiation. The crucible includes a crucible body and a nozzle disposed on a top surface of the crucible body. Except for the top surface of the crucible body, at least one side of the remaining sides of the crucible body is provided with a heat adjusting assembly. The heat adjusting assembly is configured for convecting heat radiation between the heat adjusting assembly and the crucible body. A gap exists between the heat adjusting assembly and the crucible body.
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Patent Agency Ranking
公开(公告)号：US10007175B2
公开(公告)日：2018-06-26
申请号：US15126955
申请日：2015-09-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiang Liu
CPC classification number: G03F1/38 , G03F1/00 , G03F7/039 , H01L27/127 , H01L27/1288 , H01L29/24 , H01L29/41733 , H01L29/66969
Abstract: A mask and a method for manufacturing a thin film transistor of a pixel area of an array substrate using the mask are disclosed. The mask comprises a mask body having a pattern area. The pattern area includes a photoresist partially removing area for removing photoresist partially; a photoresist completely removing area for removing photoresist completely and a first photoresist reserving area located between the photoresist partially removing area and the photoresist completely removing area and adjoining the photoresist partially removing area and the photoresist completely removing area for reserving photoresist, the first photoresist reserving area being designed to adjust a profile of a part of the photoresist corresponding to the photoresist partially removing area after exposure and development.
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37.发明授权公开(公告)号：US09947796B2
公开(公告)日：2018-04-17
申请号：US14422832
申请日：2014-04-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiang Liu
IPC: H01L29/786 , H01L27/12 , H01L21/3205 , H01L29/66 , H01L29/45 , H01L21/321 , H01L29/06
CPC classification number: H01L29/78618 , H01L21/32051 , H01L21/321 , H01L27/1225 , H01L29/06 , H01L29/45 , H01L29/66742 , H01L29/7869
Abstract: The present invention provides an oxide thin film transistor and a manufacturing method thereof, an array substrate and a display device. The oxide thin film transistor of the present invention comprises a substrate, and a gate, a gate insulation layer, an oxide semiconductor active layer, a source and a drain, which are sequentially formed on the substrate, wherein, the oxide thin film transistor further comprises a transition layer formed between the oxide semiconductor active layer and the source and between the oxide semiconductor active layer and the drain, the transition layer comprises a metal layer and a protective layer, and the protective layer is in contact with the oxide semiconductor active layer, the metal layer is arranged on the protective layer and in contact with the source and the drain, and the protective layer is made of a metal oxide.
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38.发明申请公开(公告)号：US20170139107A1
公开(公告)日：2017-05-18
申请号：US15302939
申请日：2016-02-22
Inventor： Xiang Liu
IPC: F21V8/00
CPC classification number: B29D11/00663 , B29C47/00 , G02B6/0041 , G02B6/0061 , G02B6/0065 , G02B6/0068
Abstract: The present application discloses a light guide plate comprising a light incident portion having a light incident surface for receiving light from a plurality of light sources, and a plurality of closed cavities proximal to the light incident surface and within a plurality of dark regions of the light guide plate.
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公开(公告)号：US09647013B2
公开(公告)日：2017-05-09
申请号：US13704156
申请日：2012-11-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiang Liu , Jianshe Xue
IPC: H01L29/786 , H01L27/12
CPC classification number: H01L27/1288 , H01L27/1225 , H01L29/7869
Abstract: Embodiments of the invention provide a manufacturing method of a TFT array substrate. The TFT array substrate is formed to comprise a plurality of scanning lines, a plurality of data lines and a plurality of pixel units defined by intersecting these scanning lines and these data lines with each other. Each of the pixel units comprises a TFT and a pixel electrode. The TFT is formed to comprise a gate electrode, a gate insulating layer, a metal oxide semiconductor layer used as an active layer, an etch stopping layer formed on a portion of the surface of the metal oxide semiconductor layer, a source electrode and a drain electrode. In this method, the metal oxide semiconductor layer, the source electrode and the drain electrode are formed by a same patterning process.
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公开(公告)号：US20170110490A1
公开(公告)日：2017-04-20
申请号：US15126955
申请日：2015-09-22
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xiang Liu
CPC classification number: G03F1/38 , G03F1/00 , G03F7/039 , H01L27/127 , H01L27/1288 , H01L29/24 , H01L29/41733 , H01L29/66969
Abstract: A mask and a method for manufacturing a thin film transistor of a pixel area of an array substrate using the mask are disclosed. The mask comprises a mask body having a pattern area. The pattern area includes a photoresist partially removing area for removing photoresist partially; a photoresist completely removing area for removing photoresist completely and a first photoresist reserving area located between the photoresist partially removing area and the photoresist completely removing area and adjoining the photoresist partially removing area and the photoresist completely removing area for reserving photoresist, the first photoresist reserving area being designed to adjust a profile of a part of the photoresist corresponding to the photoresist partially removing area after exposure and development.
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