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    Manufacturing method of array substrate, array substrate and display device
    33.
    发明授权
    Manufacturing method of array substrate, array substrate and display device 有权

    公开(公告)号：US10141352B2

    公开(公告)日：2018-11-27

    申请号：US15325402

    申请日：2016-03-09

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Zhanfeng Cao ,  Feng Zhang ,  Bin Zhang ,  Xiaolong He ,  Zhengliang Li ,  Wei Zhang ,  Feng Guan ,  Jincheng Gao

    IPC: H01L27/12 ,  H01L21/77

    Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.

    MICRO-NANO FLUIDIC SUBSTRATE, CHIP, PREPARATION METHOD AND SYSTEM
    36.
    发明公开
    MICRO-NANO FLUIDIC SUBSTRATE, CHIP, PREPARATION METHOD AND SYSTEM 审中-公开

    公开(公告)号：US20240261785A1

    公开(公告)日：2024-08-08

    申请号：US18018795

    申请日：2021-12-31

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Feifei Li ,  Bolin Fan ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Nianqi Yao ,  Jiayu He ,  Jie Huang ,  Kun Zhao

    IPC: B01L3/00

    CPC classification number: B01L3/502761 ,  B01L2200/0647 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/0848 ,  B01L2400/0415

    Abstract: Provided is a micro-nano fluidic substrate, a chip, a preparation method, and a system. The micro-nano fluidic substrate includes: a base; an electrode layer located on the base, the electrode layer includes a first electrode, a second electrode, and a control electrode; and a film layer located on the electrode layer and far away from the base, the film layer includes a groove layer, a nano-channel and a micro-channel, the groove layer includes a first groove, the nano-channel is located in the first groove, an orthographic projection of the nano-channel on the base at least partially coincides with an orthographic projection of the control electrode on the base, and the micro-channel is in communication with the nano-channel, the micro-channel includes a first micro-channel and a second micro-channel, and the first micro-channel is in communication with the first electrode, the second micro-channel is in communication with the second electrode.

    Semiconductor Substrate Manufacturing Method and Semiconductor Substrate
    38.
    发明申请
    Semiconductor Substrate Manufacturing Method and Semiconductor Substrate 有权

    公开(公告)号：US20230006070A1

    公开(公告)日：2023-01-05

    申请号：US17782035

    申请日：2021-05-27

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Jie Huang ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Jiayu He ,  Nianqi Yao ,  Kun Zhao ,  Feng Qu ,  Xiaochun Xu

    IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

    Abstract: A semiconductor substrate manufacturing method and a semiconductor substrate. The manufacturing method includes: forming a first semiconductor layer on the base substrate at a first temperature with a first oxide semiconductor material; forming the second semiconductor layer directly on the first semiconductor layer with a second oxide semiconductor material; and performing a patterning process such that the first semiconductor layer and the second semiconductor layer are respectively patterned into a seed layer and a first channel layer. Both the first oxide semiconductor material and the second oxide semiconductor material are capable of forming crystalline phases at a second temperature, the second temperature is less than or equal to 40° C., and the first temperature is greater than or equal to 100° C.

    Display backplane, method of manufacturing the same and display device using the same
    39.
    发明授权
    Display backplane, method of manufacturing the same and display device using the same 有权

    公开(公告)号：US11508786B2

    公开(公告)日：2022-11-22

    申请号：US16835722

    申请日：2020-03-31

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Jiayu He ,  Xue Liu ,  Zhengliang Li

    IPC: H01L27/32 ,  H01L31/105 ,  H01L31/18 ,  H01L27/12

    Abstract: The disclosure provides a display backplane, a method of manufacturing the same, and a display device using the same. The display backplane includes a substrate; a thin film transistor structure layer disposed on one side of the substrate and including thin film transistors, a gate insulating layer, and an interlayer dielectric layer, where an etching rate of the interlayer dielectric layer carried out under an HF atmosphere condition is less than 2 Å/S; and photosensitive devices spaced apart from the thin film transistor structure layer and disposed on one side of the thin film transistor structure layer away from the substrate. The interlayer dielectric layer has a high compactness, and can effectively block H from entering the active layer of the thin film transistor to conductorize the active layer, thus guaranteeing good optical characteristics of the thin film transistor while carrying out optical compensation.

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