公开(公告)号：US06348396B1

公开(公告)日：2002-02-19

申请号：US09702786

申请日：2000-11-01

Applicant: Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida

Inventor： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida

IPC: H01L2176

CPC classification number: H01L21/76232

Abstract: A semiconductor device having a SGI structure produced by selecting D, T and R values for satisfying the formula: D

Abstract translation: 具有SGI结构的半导体器件通过选择满足下式的D，T和R值产生：其中D是元件形成区域的宽度，T是以微米为单位的槽的热氧化量，R是 在槽的端部底部的曲率半径具有优异的性能，例如在硅衬底中的凹槽底部产生的应力减小，并且不产生异常结漏电流。

公开(公告)号：US6057241A

公开(公告)日：2000-05-02

申请号：US66757

申请日：1998-04-27

Applicant: Yasushi Matsuda ,  Hideo Miura ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Suzuki ,  Hirofumi Shimizu ,  Yasuko Yoshida ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

Inventor： Yasushi Matsuda ,  Hideo Miura ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Suzuki ,  Hirofumi Shimizu ,  Yasuko Yoshida ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC: H01L21/76 ,  H01L21/477

CPC classification number: H01L21/477 ,  H01L21/76

Abstract: A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp

Abstract translation: 蚀刻从槽4a的侧壁露出的氧化硅膜2，使氧化硅膜2朝向有源区域反向移动。 位移量被设定为等于或大于在随后的热氧化步骤中形成在凹槽4a的内壁上的氧化硅膜5的膜厚度（Tr），并且等于或小于两倍的膜 厚度（Tr）。 通过控制热处理时间使得氧化硅膜5的膜厚（Tr）大于膜的厚度（Tr），可以通过在1000℃以下的低温热处理使槽4a的肩部成圆形 氧化硅膜2的厚度（Tp）等于或小于其厚度（Tr）的三倍（Tp

公开(公告)号：US6031288A

公开(公告)日：2000-02-29

申请号：US747392

申请日：1996-11-12

Applicant: Hiromi Todorobaru ,  Hideo Miura ,  Masayuki Suzuki ,  Shinji Nishihara ,  Shuji Ikeda ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Atushi Ogishima ,  Hiroyuki Uchiyama ,  Sonoko Abe

Inventor： Hiromi Todorobaru ,  Hideo Miura ,  Masayuki Suzuki ,  Shinji Nishihara ,  Shuji Ikeda ,  Masashi Sahara ,  Shinichi Ishida ,  Hiromi Abe ,  Atushi Ogishima ,  Hiroyuki Uchiyama ,  Sonoko Abe

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L23/48

CPC classification number: H01L29/7845 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002

Abstract: A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm or, preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.

Abstract translation: 半导体器件包括硅衬底，电布线金属，形成在硅衬底上的绝缘膜，形成在用于将硅衬底和电布线金属彼此连接的绝缘膜中的多个接触孔，以及硅化钛 膜在接触孔中形成。 硅化钛膜的厚度为10nm〜120nm，优选为20nm〜84nm。 半导体区域和电布线金属通过硅化钛膜彼此连接。

公开(公告)号：US6030865A

公开(公告)日：2000-02-29

申请号：US66763

申请日：1998-04-28

Applicant: Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

Inventor： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC: G11C11/412 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

CPC classification number: H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/0207 ,  H01L2924/0002 ,  Y10S257/903

Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Abstract translation: 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

公开(公告)号：US5834851A

公开(公告)日：1998-11-10

申请号：US460641

申请日：1995-06-02

Applicant: Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

Inventor： Shuji Ikeda ,  Satoshi Meguro ,  Soichiro Hashiba ,  Isamu Kuramoto ,  Atsuyoshi Koike ,  Katsuro Sasaki ,  Koichiro Ishibashi ,  Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Nobuyuki Moriwaki ,  Shigeru Takahashi ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Seigou Yukutake

IPC: H01L27/11

CPC classification number: H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.

Abstract translation: 这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。 驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。 驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。 字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。 存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。 由两个字线限定的区域配置有两个驱动MISFET和源极线。 源极线由与字线的导电层相同的导电层形成。 互补数据线的各个数据线由与字线和源极线不同的导电层形成。 字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线 系统：采用双字线系统使用的子字线。

公开(公告)号：US5754467A

公开(公告)日：1998-05-19

申请号：US451117

申请日：1995-05-25

Applicant: Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

Inventor： Shuji Ikeda ,  Toshiaki Yamanaka ,  Kenichi Kikushima ,  Shinichiro Mitani ,  Kazushige Sato ,  Akira Fukami ,  Masaya Iida ,  Akihiro Shimizu

IPC: G11C11/412 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00 ,  H01L25/00 ,  H01L29/76

CPC classification number: H01L27/11 ,  G11C11/4125 ,  H01L21/76895 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/1104 ,  G11C11/412 ,  Y10S257/904

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.

Abstract translation: 一种完整的CMOS型SRAM，其存储单元由六个MISFET组成，其中一对用于连接CMOS反相器的输入/输出端的局部布线由难熔金属硅化物层形成，该难熔金属硅化物层形成在构成个体的第一导电层上 存储单元的驱动MISFET，转移MISFET和负载MISFET的栅极电极，其中形成在局部布线上的参考电压线被布置成叠加在局部布线上以形成电容器。 电容器通过将局部布线叠置在第一导电层上而形成在局部布线和第一导电层之间。 此外，通过使用诸如硅化结构的电阻降低的结构形成局部布线。 此外，公开了用于降低转移MISFET的栅电极的电阻和用于形成局部布线的处理的处理。

公开(公告)号：US5610856A

公开(公告)日：1997-03-11

申请号：US610185

申请日：1996-03-04

Applicant: Keiichi Yoshizumi ,  Satoru Haga ,  Shuji Ikeda ,  Kiichi Makuta ,  Takeshi Fukazawa

Inventor： Keiichi Yoshizumi ,  Satoru Haga ,  Shuji Ikeda ,  Kiichi Makuta ,  Takeshi Fukazawa

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/40

CPC classification number: H01L27/1112 ,  Y10S257/904

Abstract: An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.

Abstract translation: 当使用与衬垫层相同层的Al布线精细地构成用于分流的接地电压线时，由于采用这样的布局，使得电阻增加和电迁移阻抗的降低最小化： 在连接到互补数据线的一个（数据线）的衬垫层中的连接孔24,26的布置以及连接到互补数据线的另一个（数据线条）的焊盘层中的连接孔的布置是： 沿着互补数据线延伸的方向在SRAM中的每两位存储器单元互相反相。

公开(公告)号：US5543652A

公开(公告)日：1996-08-06

申请号：US98893

申请日：1993-07-29

Applicant: Shuji Ikeda ,  Makoto Saeki

Inventor： Shuji Ikeda ,  Makoto Saeki

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L29/88 ,  H01L27/01 ,  H01L29/76

CPC classification number: H01L29/78696 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

Abstract: Negative characteristic MISFETs, which are of the same channel conductivity type and which have different threshold voltages, are formed in a doped silicon thin film deposited over a substrate and are connected in channel-to-channel series with each other. The pair of series-connected negative characteristic MISFETs, a resistive element, an information storage capacitive element and a transfer MISFET constitute an SRAM memory cell. Equivalently, a negative characteristic MISFET having a current-voltage characteristic defined by a negative resistance curve can be used in lieu of the pair of series-connected negative characteristic MISFETs in the formation of the individual memory cells of the SRAM. The negative resistance curve of the negative characteristic MISFET is shaped such that the linear current-voltage characteristic curve corresponding to the resistive element of the memory cell intersects the negative resistance curve at at least three location points. The negative characteristic MISFET, like the pair of series-connected negative characteristic MISFETs, has an active region formed in a doped thin film silicon (polycrystalline silicon) layer insulatedly above a substrate main surface. The resistive element is also formed in a thin film silicon layer either integrally with the negative characteristic MISFET or in a separate thin film silicon layer and in series electrical connection with the negative characteristic MISFET.

Abstract translation: 具有相同沟道导电类型且具有不同阈值电压的负特性MISFET形成在沉积在衬底上并以通道间通道串联连接的掺杂硅薄膜中。 一对串联负特性MISFET，电阻元件，信息存储电容元件和转移MISFET构成SRAM存储单元。 等效地，可以使用由负电阻曲线限定的电流 - 电压特性的负特性MISFET来代替在SRAM的各个存储单元的形成中的一对串联负特性MISFET。 负特性MISFET的负电阻曲线被成形为使得对应于存储单元的电阻元件的线性电流 - 电压特性曲线在至少三个位置点处与负电阻曲线相交。 负极特性MISFET，像一对串联连接的负特性MISFET一样，具有在衬底主表面上绝缘的掺杂薄膜硅（多晶硅）层中形成的有源区。 电阻元件也与负特性MISFET或单独的薄膜硅层整体地形成在薄膜硅层中，并与负特性MISFET串联电连接。

公开(公告)号：US5396100A

公开(公告)日：1995-03-07

申请号：US861366

申请日：1992-03-31

Applicant: Kohji Yamasaki ,  Nobuyuki Moriwaki ,  Shuji Ikeda ,  Hideaki Nakamura ,  Shigeru Honjo

Inventor： Kohji Yamasaki ,  Nobuyuki Moriwaki ,  Shuji Ikeda ,  Hideaki Nakamura ,  Shigeru Honjo

IPC: H01L27/02 ,  H01L27/11 ,  H01L29/76 ,  H01L23/552 ,  H01L27/10

CPC classification number: H01L27/1108 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S257/903

Abstract: Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

Abstract translation: 这里公开了一种半导体集成电路器件，其具有由矩阵形状规则地排列的存储单元形成的存储器阵列或存储器垫。 在存储器单元的图案化中断或中断的器件的区域中的存储器阵列或存储单元的端部或内部，形成用于调节具有图案的存储单元的元件隔离绝缘膜的形状 使得与存储单元的图形不间断规则形式的装置区域中用于调节存储单元的元件隔离绝缘膜的形状基本相同。 在与存储区域相关联的规则图案的芯片正面上的位置中断的情况下，形成具有与布置在位置的端部的栅电极的形状基本相同的形状的虚设图案，其中规则图案 被中断。

公开(公告)号：US5122857A

公开(公告)日：1992-06-16

申请号：US638768

申请日：1991-01-08

Applicant: Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

Inventor： Shuji Ikeda ,  Katsuro Sasaki ,  Kouichi Nagasawa ,  Satoshi Meguro

IPC: H01L21/768 ,  G11C11/41 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11

CPC classification number: H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S257/906

Abstract: A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM further has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.