公开(公告)号：US08969935B2

公开(公告)日：2015-03-03

申请号：US13439423

申请日：2012-04-04

申请人： Hiroyuki Uchiyama

发明人： Hiroyuki Uchiyama

IPC分类号： H01L27/108 ,  H01L49/02

CPC分类号： H01L27/10814 ,  H01L27/10817 ,  H01L28/86 ,  H01L28/90

摘要： Disclosed herein is a device that includes a semiconductor substrate having a first area, a plurality of cell transistors arranged on the first area of the semiconductor substrate, and a plurality of cell capacitors each coupled to an associated one of the cell transistors, the cell capacitors being provided so as to overlap with one another on the first area.

摘要翻译： 本文公开了一种器件，其包括具有第一区域的半导体衬底和布置在半导体衬底的第一区域上的多个单元晶体管，以及多个单元电容器，每个单元电容器耦合到相关联的一个单元晶体管，单元电容器 被设置为在第一区域上彼此重叠。

公开(公告)号：US08912537B2

公开(公告)日：2014-12-16

申请号：US13642612

申请日：2011-04-22

申请人： Hironori Wakana ,  Tetsufumi Kawamura ,  Hiroyuki Uchiyama ,  Kuniharu Fujii

发明人： Hironori Wakana ,  Tetsufumi Kawamura ,  Hiroyuki Uchiyama ,  Kuniharu Fujii

IPC分类号： H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7869

摘要： Disclosed is an oxide semiconductor layer (13) which forms a channel for a thin-film transistor and which includes at least In and oxygen and one or more types of elements from among Zn, Cd, Al, Ga, Si, Sn, Ce, and Ge. A high concentration region (13d) is disposed on one section of the oxide semiconductor layer (13), whereby said region has a maximum In concentration 30 at %; or higher than other regions on the oxide semiconductor layer (13). The film thickness of the oxide semiconductor layer (13) is 100 nm max., and the film thickness of the high concentration region (13d) is 20 nm max. or, preferably, 6 nm max. This enables a thin-film transistor with a sub-threshold slope of 100 mV/decade max., a high on-current, and a high field effect mobility to be achieved.

摘要翻译： 公开了一种氧化物半导体层（13），其形成用于薄膜晶体管的沟道，并且至少包括In和氧，以及从Zn，Cd，Al，Ga，Si，Sn，Ce中选出的一种或多种元素， 和格。 高浓度区域（13d）设置在氧化物半导体层（13）的一个部分上，由此所述区域的最大In浓度为30原子％。 或高于氧化物半导体层（13）上的其它区域。 氧化物半导体层（13）的膜厚最大为100nm，高浓度区域（13d）的膜厚为20nm以下。 或者优选地，最多6nm。 这使得能够实现具有100mV / 10倍的次阈值斜率，高导通电流和高场效应迁移率的薄膜晶体管。

公开(公告)号：US20130187154A1

公开(公告)日：2013-07-25

申请号：US13811227

申请日：2011-07-01

申请人： Hiroyuki Uchiyama ,  Hironori Wakana

发明人： Hiroyuki Uchiyama ,  Hironori Wakana

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/78693 ,  H01L29/78696

摘要： Disclosed is a technique for suppressing fluctuation of device characteristics in thin film transistors using an oxide semiconductor film as a channel layer. In a thin film transistor using an oxide semiconductor film as a channel layer (4), said channel layer (4) is configured from an oxide semiconductor having as main materials a zinc oxide and tin oxide with introduced group IV elements or group V elements, wherein the ratio (A/B) of the impurity concentration (A) of the group IV elements or group V elements contained in the channel layer (4) and the impurity concentration (B) of the group III elements contained in the channel layer (4) satisfies A/B≦1.0, and ideally A/B≦0.3.

摘要翻译： 公开了一种抑制使用氧化物半导体膜作为沟道层的薄膜晶体管的器件特性变动的技术。 在使用氧化物半导体膜作为沟道层（4）的薄膜晶体管中，所述沟道层（4）由作为主要材料的氧化物半导体构成，具有引入IV族元素或V族元素的氧化锌和氧化锡， 其中所述沟道层（4）中包含的IV族元素或V族元素的杂质浓度（A）与包含在沟道层中的III族元素的杂质浓度（B）的比（A / B） 4）满足A / B@1.0，理想情况下A / B @ 0.3。

公开(公告)号：US20120012927A1

公开(公告)日：2012-01-19

申请号：US13183963

申请日：2011-07-15

申请人： Hiroyuki UCHIYAMA

发明人： Hiroyuki UCHIYAMA

IPC分类号： H01L29/78

CPC分类号： H01L27/10885 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

摘要： A semiconductor device includes: a cell gate trench with a bottom face and first/second side faces; a field-shield gate trench narrower than the cell gate trench; a first upper diffusion layer between the cell gate trench and the field-shield gate trench; a second upper diffusion layer on the opposite side of the cell gate trench from the first upper diffusion layer; a third upper diffusion layer on the opposite side of the field-shield gate trench from the first upper diffusion layer; a lower diffusion layer on the bottom face of the cell gate trench; first and second storage elements electrically connected to the first and second upper diffusion layers, respectively; a bit line electrically connected to the lower diffusion layer; a word line covering first and second side faces via a gate insulating film; and a field-shield gate electrode in the field-shield gate trench via a gate insulating film.

摘要翻译： 半导体器件包括：具有底面和第一/第二侧面的单元栅极沟槽; 场屏蔽栅极沟槽比单元栅极沟槽窄; 在单元栅极沟槽和场屏蔽栅极沟槽之间的第一上部扩散层; 在与第一上部扩散层相对的单元栅极沟槽的相对侧上的第二上部扩散层; 在所述场屏蔽栅极沟槽的与所述第一上扩散层相反的一侧上的第三上扩散层; 在单元栅极沟槽的底面上的下扩散层; 第一和第二存储元件分别电连接到第一和第二上扩散层; 电连接到下扩散层的位线; 经由栅极绝缘膜覆盖第一和第二侧面的字线; 以及通过栅极绝缘膜在场屏蔽栅极沟槽中的场屏蔽栅电极。

公开(公告)号：US07977675B2

公开(公告)日：2011-07-12

申请号：US12423053

申请日：2009-04-14

申请人： Tetsufumi Kawamura ,  Takeshi Sato ,  Mutsuko Hatano ,  Hiroyuki Uchiyama

发明人： Tetsufumi Kawamura ,  Takeshi Sato ,  Mutsuko Hatano ,  Hiroyuki Uchiyama

IPC分类号： H01L29/12

CPC分类号： H01L27/1225 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/7869

摘要： A metallic oxide semiconductor device with high performance and small variations. It is a field effect transistor using a metallic oxide film for the channel, which includes a channel region and a source region and comprises a drain region with a lower oxygen content than the channel region in the metallic oxide, in which the channel region exhibits semiconductor characteristics and the oxygen content decreases with depth below the surface.

摘要翻译： 具有高性能和小变化的金属氧化物半导体器件。 它是一种使用金属氧化物膜作为沟道的场效应晶体管，其包括沟道区和源极区，并且包括具有比金属氧化物中的沟道区更低的氧含量的漏区，其中沟道区表现出半导体 特性和氧含量随着表面深度的减小而减小。

公开(公告)号：US20100187698A1

公开(公告)日：2010-07-29

申请号：US12694707

申请日：2010-01-27

申请人： Hiroyuki UCHIYAMA

发明人： Hiroyuki UCHIYAMA

IPC分类号： H01L23/522 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first wiring layer, a first interlayer insulating film over the first wiring layer, a second wiring layer crossing the first wiring layer and provided on the first interlayer insulating film, a second interlayer insulating film over the second wiring layer, and a via conductor electrically connecting the first wiring layer and the second wiring layer together. The second wiring layer includes a space separating the second wiring layer into pieces, the space being located at a position where the second wiring layer crosses the first wiring layer. The via conductor passes through the separation space such that the separated pieces of the second wiring layer are electrically connected together, the via conductor extending to the first wiring layer through the second interlayer insulating film and the first interlayer insulating film.

摘要翻译： 半导体器件包括第一布线层，第一布线层上的第一层间绝缘膜，与第一布线层交叉并设置在第一层间绝缘膜上的第二布线层，在第二布线层上的第二层间绝缘膜，以及 通孔导体将第一布线层和第二布线层电连接在一起。 第二布线层包括将第二布线层分成片的空间，该空间位于第二布线层与第一布线层交叉的位置。 通孔导体通过分离空间，使得第二布线层的分离片电连接在一起，通孔导体通过第二层间绝缘膜和第一层间绝缘膜延伸到第一布线层。

公开(公告)号：US07724272B2

公开(公告)日：2010-05-25

申请号：US12207100

申请日：2008-09-09

申请人： Hiroyuki Uchiyama

发明人： Hiroyuki Uchiyama

IPC分类号： B41J2/44 ,  G03B17/24

CPC分类号： H04N1/00257 ,  H04N1/00249 ,  H04N2201/0082 ,  H04N2201/0084 ,  H04N2201/0089

摘要： A print unit for transferring an image to a photosensitive medium is provided, and the print unit includes an intercepting member for intercepting light; a first plane light-emitting member for forming a first image by emitting light, provided on one side of the intercepting member; a second plane light-emitting member for forming a second image by emitting light, provided on the other side of the intercepting member; and a control unit for controlling light-emission of the first and second surface emitting members and transferring at least one or more of images to the photosensitive medium.

摘要翻译： 提供了用于将图像转印到感光介质的打印单元，并且打印单元包括用于遮挡光的遮挡构件; 用于通过发射光形成第一图像的第一平面发光部件，设置在所述拦截部件的一侧; 用于通过发射光形成第二图像的第二平面发光部件，设置在所述拦截部件的另一侧; 以及控制单元，用于控制第一和第二表面发射构件的发光并将至少一个或多个图像转印到感光介质。

公开(公告)号：US20090179200A1

公开(公告)日：2009-07-16

申请号：US12318452

申请日：2008-12-30

申请人： Shinichi Saito ,  Hiroyuki Uchiyama ,  Toshiyuki Mine

发明人： Shinichi Saito ,  Hiroyuki Uchiyama ,  Toshiyuki Mine

IPC分类号： H01L33/00

CPC分类号： H01L27/156 ,  H01L33/16 ,  H01L33/34

摘要： A self emission silicon emission display is provided at a low price, which contains silicon and oxygen which exist in abundance on the earth as the main component and which can be easily formed by conventional silicon process. A light emission element includes a first electrode for injecting electrons, a second electrode for injecting holes, and a light emission part electrically connected to the first electrode and the second electrode, where the light emission part includes amorphous or polycrystalline silicon consisting of a single layer or plural layers and where the dimension of the silicon in at least one direction is controlled to be several nanometers.

摘要翻译： 以低价格提供自发射硅发射显示器，其包含以地球上丰富地存在的硅和氧作为主要成分，并且可以通过常规硅工艺容易地形成。 发光元件包括用于注入电子的第一电极，用于注入空穴的第二电极和与第一电极和第二电极电连接的发光部分，其中发光部分包括由单层组成的非晶或多晶硅 或多个层，并且其中至少一个方向上的硅的尺寸被控制为几纳米。

公开(公告)号：US20070161177A1

公开(公告)日：2007-07-12

申请号：US11652072

申请日：2007-01-11

申请人： Hiroyuki Uchiyama

发明人： Hiroyuki Uchiyama

IPC分类号： H01L21/8244

CPC分类号： H01L28/90 ,  H01L27/10897

摘要： A semiconductor device of the present invention comprises a memory cell area having memory cells arranged in an array form, each of which includes a capacitor for storing data and a peripheral circuit area for accessing the memory cell area. The peripheral circuit area is provided with a plurality of wiring layers and each of the memory cells has a capacitor. The capacitor is comprised of a plate electrode, a capacitive insulating film formed on a side wall of an opening formed through the plate electrode, and a storage electrode embedded in the opening in which the capacitive insulating film is formed on the side wall, such that the plate electrodes, the capacitive insulating films, and the storage electrodes of the memory cells are arranged in correspondence to the plurality of wiring layers, and the storage electrodes are connected to one another.

摘要翻译： 本发明的半导体器件包括具有以阵列形式布置的存储单元的存储单元区域，每个存储单元包括用于存储数据的电容器和用于访问存储器单元区域的外围电路区域。 外围电路区域设置有多个布线层，并且每个存储单元具有电容器。 该电容器包括：平板电极，形成在通过该平板电极形成的开口的侧壁上的电容绝缘膜;以及嵌入在该侧壁上形成电容绝缘膜的开口中的存储电极，使得 存储单元的平板电极，电容绝缘膜和存储电极相对于多个布线层布置，并且存储电极彼此连接。

公开(公告)号：US07224034B2

公开(公告)日：2007-05-29

申请号：US10978469

申请日：2004-11-02

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了一种通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术：在p上的栅极绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜 （半导体衬底），帽绝缘膜，W膜和WN膜被蚀刻，并且进行其下面的多晶硅膜的过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止