公开(公告)号：US20140174026A1

公开(公告)日：2014-06-26

申请号：US14235323

申请日：2012-08-21

Applicant: Kazuo Iimori ,  Akira Takamatsu

Inventor： Kazuo Iimori ,  Akira Takamatsu

IPC: B65B1/30

CPC classification number: B65B1/30 ,  A61J7/0069 ,  B65B9/06 ,  B65B57/12 ,  B65B59/02 ,  B65B61/025 ,  G06F19/3456 ,  G06F19/3462 ,  G06Q50/24

Abstract: A packaging device eliminating waste of package paper can be provided. The packaging device includes: a computer that creates one packaging data based on prescription data regarding a plurality of patients belonging to the same group; and a packaging machine that packages a drug based on the packaging data created by the computer.

Abstract translation: 可以提供消除包装纸浪费的包装装置。 包装装置包括：计算机，其基于关于属于同一组的多个患者的处方数据来创建一个包装数据; 以及基于由计算机创建的包装数据来包装药物的包装机。

公开(公告)号：US20050196935A1

公开(公告)日：2005-09-08

申请号：US11108827

申请日：2005-04-19

Applicant: Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

Inventor： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC: H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76235 ,  H01L29/78

Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

公开(公告)号：US20050148155A1

公开(公告)日：2005-07-07

申请号：US11055745

申请日：2005-02-11

Applicant: Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

Inventor： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC: H01L21/76 ,  G02B17/00 ,  G02B21/00 ,  G02B23/00 ,  H01L21/302 ,  H01L21/312 ,  H01L21/316 ,  H01L21/461 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L21/76229 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/3125 ,  H01L21/31612 ,  H01L27/0211 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10894

Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patterns in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited

Abstract translation: 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对较大的隔离区域中形成虚拟图案的步骤

公开(公告)号：US06881646B2

公开(公告)日：2005-04-19

申请号：US10392916

申请日：2003-03-21

Applicant: Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

Inventor： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC: H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76235 ,  H01L29/78

Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Abstract translation: 一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。 通过减小半导体衬底上的元件隔离槽的槽上边缘周围的应力产生，从而优化元件隔离槽的形状并使器件更精细并提高器件电气特性来制造器件。

公开(公告)号：US6057241A

公开(公告)日：2000-05-02

申请号：US66757

申请日：1998-04-27

Applicant: Yasushi Matsuda ,  Hideo Miura ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Suzuki ,  Hirofumi Shimizu ,  Yasuko Yoshida ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

Inventor： Yasushi Matsuda ,  Hideo Miura ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Suzuki ,  Hirofumi Shimizu ,  Yasuko Yoshida ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC: H01L21/76 ,  H01L21/477

CPC classification number: H01L21/477 ,  H01L21/76

Abstract: A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp

Abstract translation: 蚀刻从槽4a的侧壁露出的氧化硅膜2，使氧化硅膜2朝向有源区域反向移动。 位移量被设定为等于或大于在随后的热氧化步骤中形成在凹槽4a的内壁上的氧化硅膜5的膜厚度（Tr），并且等于或小于两倍的膜 厚度（Tr）。 通过控制热处理时间使得氧化硅膜5的膜厚（Tr）大于膜的厚度（Tr），可以通过在1000℃以下的低温热处理使槽4a的肩部成圆形 氧化硅膜2的厚度（Tp）等于或小于其厚度（Tr）的三倍（Tp

公开(公告)号：US20070114631A1

公开(公告)日：2007-05-24

申请号：US11653321

申请日：2007-01-16

Applicant: Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

Inventor： Hidenori Sato ,  Norio Suzuki ,  Akira Takamatsu ,  Hiroyuki Maruyama ,  Takeshi Saikawa ,  Katsuhiko Hotta ,  Hiroyuki Ichizoe

IPC: H01L29/00

CPC classification number: H01L21/76224 ,  H01L27/0207 ,  H01L27/10894

Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

Abstract translation: 一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置， 用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽 沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。 该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

公开(公告)号：US4201843A

公开(公告)日：1980-05-06

申请号：US881279

申请日：1978-02-27

Applicant: Rokuro Okamoto ,  Tsumoru Fukumoto ,  Akira Takamatsu ,  Tomio Takeuchi

Inventor： Rokuro Okamoto ,  Tsumoru Fukumoto ,  Akira Takamatsu ,  Tomio Takeuchi

IPC: C07H17/08 ,  C12P19/62 ,  C12R1/55

CPC classification number: C07H17/08 ,  C12P19/62 ,  C12R1/465 ,  C12R1/55 ,  Y10S435/898

Abstract: New tylosin derivatives having at least one acyl group at the 3- and 4"-positions of tylosin, and the acid addition salts thereof, which inhibit the growth of various microorganisms including drug-resistant bacterial isolants and which produce high blood levels through oral administration are produced by a biochemical reaction using the microorganisms of the genus Streptomyces which are selected for their newly-found ability to acylate at least one of the 3- and 4"-positions of macrolide antibiotics; they are recovered from the reacted mixture by conventional methods for recovering macrolide antibiotics.

Abstract translation: 在泰乐菌素的3和4“位具有至少一个酰基的新泰乐菌素衍生物及其酸加成盐，其抑制各种微生物生长，包括耐药性细菌分离物，并通过口服产生高血药浓度 通过使用由链霉菌属（Streptomyces）属的微生物生物化学反应来产生施用，所述微生物被选择用于其新发现的能够酰化大环内酯类抗生素的3-和4-位中的至少一个的能力; 它们通过用于回收大环内酯类抗生素的常规方法从反应混合物中回收。

公开(公告)号：US4091097A

公开(公告)日：1978-05-23

申请号：US769482

申请日：1977-02-17

Applicant: Hamao Umezawa ,  Tomio Takeuchi ,  Akira Takamatsu ,  Kenji Kayahara

Inventor： Hamao Umezawa ,  Tomio Takeuchi ,  Akira Takamatsu ,  Kenji Kayahara

IPC: A61K31/235 ,  A61K31/60

CPC classification number: A61K31/235 ,  A61K31/60

Abstract: Compounds having the general formula ##STR1## wherein R.sup.2 is substituted either at the 4'-position or at the 5'-position and is hydrogen, fluoro, bromo, chloro, hydroxy or lower alkyl; R.sup.3 is chloro, bromo or lower alkyl; R.sup.4 is hydroxy, amino or lower alkoxy, and Z is hydrogen or lower alkyl and the nontoxic, pharmaceutically acceptable metal salts of said compounds when Z is hydrogen exhibit strong activities in inhibiting histidine decarboxylase and anthine oxidase.

Abstract translation: 具有通式“IMAGE”的化合物，其中R 2在4位或5位被取代，为氢，氟，溴，氯，羟基或低级烷基; R3是氯，溴或低级烷基; R 4是羟基，氨基或低级烷氧基，Z是氢或低级烷基，当Z是氢时，所述化合物的无毒的药学上可接受的金属盐在抑制组氨酸脱羧酶和蒽氧化酶中表现出强烈的活性。

公开(公告)号：US4072753A

公开(公告)日：1978-02-07

申请号：US769481

申请日：1977-02-17

Applicant: Hamao Umezawa ,  Tomio Takeuchi ,  Akira Takamatsu ,  Shunro Mori

Inventor： Hamao Umezawa ,  Tomio Takeuchi ,  Akira Takamatsu ,  Shunro Mori

IPC: A61K31/60 ,  A61K31/235 ,  A61K31/24 ,  A61K31/245

CPC classification number: A61K31/60

Abstract: Compounds having the formula ##STR1## (the meanings of R.sup.1, R.sup.2, R.sup.3, R.sup.4 and R.sup.5 are indicated hereinafter) exhibit suppressive activity to various immune responses and can be employed in the therapy of immunological diseases, especially autoimmune diseases.One example is 3',5'-dichloro-2,4'-diacetoxybenzanilide having the formula ##STR2## and another is 3',5'-dichloro-2,4'-dibenzoyloxyanilide having the formula ##STR3##

Abstract translation: 具有式“IMAGE”（R1，R2，R3，R4和R5的含义的化合物）在下文中表示的化合物对各种免疫反应表现出抑制活性，可用于免疫疾病，特别是自身免疫性疾病的治疗。

公开(公告)号：US4055468A

公开(公告)日：1977-10-25

申请号：US738193

申请日：1976-11-03

Applicant: Hamao Umezawa ,  Tomio Takeuchi ,  Takaaki Aoyagi ,  Akira Takamatsu ,  Taiji Inui ,  Hiroshi Tone ,  Hajime Morishima

Inventor： Hamao Umezawa ,  Tomio Takeuchi ,  Takaaki Aoyagi ,  Akira Takamatsu ,  Taiji Inui ,  Hiroshi Tone ,  Hajime Morishima

IPC: C07K5/02 ,  C12D13/06

CPC classification number: C07K5/0205 ,  Y10S435/822 ,  Y10S435/829 ,  Y10S435/834 ,  Y10S435/835 ,  Y10S435/839 ,  Y10S435/842 ,  Y10S435/849 ,  Y10S435/855 ,  Y10S435/859 ,  Y10S435/874 ,  Y10S435/884 ,  Y10S435/91 ,  Y10S435/911 ,  Y10S435/929

Abstract: A novel physiologically active peptide Val--X--Ala--X, in which X is 4-amino-3-hydroxy-6-methylheptanoic acid, which is prepared from R--Val--Val--X--Ala--X by the action of a microbial enzyme, N-acyl derivatives thereof which are produced by acylating said new peptide, and the processes for producing thereof and the microbial enzyme are disclosed.

Abstract translation: 一种新的生理活性肽Val-X-Ala-X，其中X是4-氨基-3-羟基-6-甲基庚酸，其由R-Val-Val-X-Ala-X通过 公开了通过酰化所述新肽产生的微生物酶及其N-酰基衍生物及其制备方法和微生物酶。