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72 条记录 (耗时 0.022 秒)

    Method for scalable, low-cost polysilicon capacitor in a planar DRAM
    32.
    发明授权
    Method for scalable, low-cost polysilicon capacitor in a planar DRAM 失效
    在平面DRAM中可扩展的低成本多晶硅电容器的方法

    公开(公告)号：US07087486B2

    公开(公告)日：2006-08-08

    申请号：US10963228

    申请日：2004-10-12

    申请人： Jeffrey S. Brown ,  Randy W. Mann

    发明人： Jeffrey S. Brown ,  Randy W. Mann

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10861 ,  H01L27/0207 ,  H01L27/1203

    摘要： Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.

    摘要翻译： 提供了增加电容而不损及电池区的电容器结构及其制造方法。 第一电容器结构包括存在于半导体衬底中的孔中的绝缘材料，其中每个电容器孔的底壁上的绝缘材料与每个孔的侧壁相比较厚。 在另一个电容器结构中，提供深电容器孔，其具有存在于每个孔下方的隔离植入区。

    FinFET SRAM cell using low mobility plane for cell stability and method for forming
    33.
    发明授权
    FinFET SRAM cell using low mobility plane for cell stability and method for forming 失效
    FinFET SRAM单元使用低迁移率平面进行电池稳定性和成型方法

    公开(公告)号：US07087477B2

    公开(公告)日：2006-08-08

    申请号：US10987532

    申请日：2004-11-12

    申请人： David M. Fried ,  Randy W. Mann ,  K. Paul Muller ,  Edward J. Nowak

    发明人： David M. Fried ,  Randy W. Mann ,  K. Paul Muller ,  Edward J. Nowak

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785 ,  Y10S257/903

    摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.

    摘要翻译： 本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。 本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。 如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。 这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。 在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。 用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。 如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作。

    Zero threshold voltage pFET and method of making same
    35.
    发明授权
    Zero threshold voltage pFET and method of making same 失效
    零阈值电压pFET及其制作方法

    公开(公告)号：US07005334B2

    公开(公告)日：2006-02-28

    申请号：US10845835

    申请日：2004-05-14

    申请人： Jeffrey S. Brown ,  Chung H. Lam ,  Randy W. Mann ,  Jeffery H. Oppold

    发明人： Jeffrey S. Brown ,  Chung H. Lam ,  Randy W. Mann ,  Jeffery H. Oppold

    IPC分类号： H01L21/336

    CPC分类号： H01L29/1037 ,  H01L21/823412 ,  H01L21/823493 ,  H01L29/78

    摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).

    摘要翻译： 零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。 这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。 可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与 彼此隔开p型衬底材料的口袋。 在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。

    High mobility transistors in SOI and method for forming
    37.
    发明授权
    High mobility transistors in SOI and method for forming 有权
    SOI中的高迁移率晶体管和形成方法

    公开(公告)号：US06624478B2

    公开(公告)日：2003-09-23

    申请号：US09683656

    申请日：2002-01-30

    申请人： Brent A. Anderson ,  Xavier Baie ,  Randy W. Mann ,  Edward J. Nowak ,  Jed H. Rankin

    发明人： Brent A. Anderson ,  Xavier Baie ,  Randy W. Mann ,  Edward J. Nowak ,  Jed H. Rankin

    IPC分类号： H01L2701

    CPC分类号： H01L29/7842 ,  H01L21/84 ,  H01L27/1203

    摘要： The present invention provides a device design and method for forming Field Effect Transistors (FETs) that have improved performance without negative impacts to device density. The present invention forms high-gain p-channel transistors by forming them on silicon islands where hole mobility has been increased. The hole mobility is increased by applying physical straining to the silicon islands. By straining the silicon islands, the hole mobility is increased resulting in increased device gain. This is accomplished without requiring an increase in the size of the devices, or the size of the contacts to the devices.

    摘要翻译： 本发明提供了一种用于形成场效应晶体管（FET）的器件设计和方法，其具有改进的性能而不会对器件密度造成负面影响。 本发明通过在硅岛上形成高增益p沟道晶体管，其中空穴迁移率已经增加。 通过对硅岛施加物理应变来增加空穴迁移率。 通过拉伸硅岛，空穴迁移率增加，导致器件增益增加。 这是在不需要增加设备尺寸或者与设备的触点的尺寸的情况下实现的。

    Method for forming implants in semiconductor fabrication
    39.
    发明授权
    Method for forming implants in semiconductor fabrication 失效
    在半导体制造中形成植入物的方法

    公开(公告)号：US06395624B1

    公开(公告)日：2002-05-28

    申请号：US09253952

    申请日：1999-02-22

    申请人： James A. Bruce ,  Randy W. Mann

    发明人： James A. Bruce ,  Randy W. Mann

    IPC分类号： H01L21336

    CPC分类号： H01L21/223 ,  H01L21/268 ,  Y10S438/952

    摘要： The present invention provides a novel method of forming implants with Projection Gas-Immersion Laser Doping (PGILD) process that overcomes the disadvantages of the prior art methods. In particular, the preferred method applies a reflective coating over features before the application of the PGILD laser. The reflective coating lowers the amount of heat absorbed by the features, improving the reliability of the fabrication process. The preferred method is particularly applicable to the fabrication of field effect transistors (FETs). In this application, a gate stack is formed, and a reflective coating is over the gate stack. An anti-reflective coating (ARC) is then applied over the reflective coating. The anti-reflective coating reduces variability of the photolithographic process used to pattern the gate stack. After the gate stack is patterned, the anti-reflective coating is removed, leaving the reflective coating on the gate stack. The PGILD process can then be used to form source/drain doped regions on the transistors. The reflective coating reduces the amount of heat absorbed by the gate stack, and thus provides an improved method for fabricating transistors.

    摘要翻译： 本发明提供了一种克服现有技术方法的缺点的用投影气体浸渍激光掺杂（PGILD）工艺形成植入物的新方法。 特别地，优选的方法在施加PGILD激光器之前对反射涂层施加特征。 反射涂层降低了由特征吸收的热量，提高了制造工艺的可靠性。 优选的方法特别适用于场效应晶体管（FET）的制造。 在这种应用中，形成栅极叠层，并且反射涂层在栅极叠层上方。 然后将抗反射涂层（ARC）涂覆在反射涂层上。 抗反射涂层降低了用于对栅极堆叠进行图案化的光刻工艺的变化。 在栅极堆叠被图案化之后，去除抗反射涂层，使反射涂层留在栅极叠层上。 然后可以使用PGILD工艺在晶体管上形成源极/漏极掺杂区域。 反射涂层减少了栅叠层吸收的热量，因此提供了一种制造晶体管的改进方法。