公开(公告)号：US4887136A

公开(公告)日：1989-12-12

申请号：US110462

申请日：1987-10-20

Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima

Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10829 ,  Y10S257/911

Abstract: A dynamic semiconductor memory device comprising a substrate having one trench including two capacitors for memory cell capacitances of two bits, and two elements such as transistors for reading, writing, and storing information represented by charge, arranged symmetrically at the central portion of the trench so as to correspond to the memory cells for two bits, and a field oxide film formed at the center of the trench on the bottom and on the side walls for separating the capacitors and elements.

Abstract translation: 一种动态半导体存储器件，包括具有一个沟槽的衬底，该沟槽包括用于存储器单元电容两位的两个电容器，以及用于读取，写入和存储由电荷表示的信息的晶体管的两个元件，其对称地布置在沟槽的中心部分处 对应于两位的存储单元，以及形成在底部和侧壁上的沟槽中心的场氧化膜，用于分离电容器和元件。

公开(公告)号：US4839864A

公开(公告)日：1989-06-13

申请号：US163015

申请日：1988-03-02

Applicant: Kazuyasu Fujishima

Inventor： Kazuyasu Fujishima

IPC: G11C29/00 ,  G11C29/04 ,  H01L27/10

CPC classification number: G11C29/80

Abstract: A semiconductor memory device comprises a plurality of memory cells arranged in a plurality of rows and columns, a plurality of row decoders for selecting one row of the plurality of rows, spare memory cells arranged in one row and a spare decoder for selecting the spare memory cells arranged in the one row. Each of the row decoders comprises a link element which can be melted by a laser beam. A plurality of decoder state determining logical circuits are provided corresponding to the plurality of row decoders. If and when a defective memory cell exists of the memory cells arranged in one row corresponding to each of the row decoders, the link element in the row decoder is melted in advance. When the row decoder having the link element melted in advance is selected by address signals, a corresponding decoder state determining logical circuit generates an SEE signal. The spare decoder is selected in place of the row decoder by the SEE signal.

Abstract translation: 一种半导体存储器件，包括以多行排列的多个存储单元，多行行解码器，用于选择多行中的一行，排列成一行的备用存储单元和用于选择备用存储器的备用解码器 细胞排列在一排。 行解码器中的每一个包括能够被激光束熔化的连接元件。 对应于多个行解码器提供多个解码器状态确定逻辑电路。 如果存在与排列在与行解码器中的每行相对应的一行中的存储单元存在缺陷存储单元的情况下，行解码器中的链接元件预先熔化。 当通过地址信号选择具有预先熔化的链接元件的行解码器时，对应的解码器状态确定逻辑电路产生SEE信号。 通过SEE信号来选择备用解码器来代替行解码器。

公开(公告)号：US4833650A

公开(公告)日：1989-05-23

申请号：US34094

申请日：1987-04-02

Applicant: Kazutoshi Hirayama ,  Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Hideto Hidaka

Inventor： Kazutoshi Hirayama ,  Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Hideto Hidaka

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096

CPC classification number: G11C7/22 ,  G11C11/4096 ,  G11C7/1033 ,  G11C7/1045

Abstract: A semiconductor memory device includes a plurality of operation mode control circuits provided on a memory chip of the device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuits provided on the memory chip, each of the operation mode selection circuits having a fuse element and a bonding pad for selecting one of the plurality of the operation mode control circuits when the fuse element is cut off or the bonding pad is selectively wired, so that various functions can be selectively effected on the same chip.

Abstract translation: 半导体存储器件包括设置在该器件的存储器芯片上的多个操作模式控制电路，用于分别执行至少包括静态列模式，高速页模式和半字节模式的对应多个写/读操作模式， 以及设置在所述存储芯片上的多个操作模式选择电路，每个所述操作模式选择电路具有熔丝元件和用于在所述熔丝元件被切断时选择所述多个所述操作模式控制电路中的一个的焊盘， 接合焊盘是有选择地布线的，从而可以在同一芯片上选择性地实现各种功能。

公开(公告)号：US4833645A

公开(公告)日：1989-05-23

申请号：US929367

申请日：1986-11-12

Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima

Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1085 ,  H01L27/10805

Abstract: In the semiconductor memory device according to the present invention, a n type drain diffused region (9a) to be connected to a bit line (12) is formed on a p type semiconductor substrate (1) and a n type source diffused region (9b) is formed with a prescribed spacing from the n type drain region (9a). On the p type silicon substrate (1), a p type diffused region (16a) of high impurity density and p type diffused region (16b) of high impurity density are formed in such a manner that they are in contact with the n type drain diffused region (9a) and the n type source diffused region (9b), respectively, but not in the channel region of the n channel MOS transistor (18). Consequently, the .alpha. particle-generated charges can be decreased without changing the threshold voltage of the transfer gate transistor.

Abstract translation: 在本发明的半导体存储装置中，在p型半导体基板（1）上形成与位线（12）连接的漏型扩散区域（9a），形成型源扩散区域（9b） 与n型漏极区域（9a）具有规定的间隔。 在p型硅基板（1）上，以高杂质密度的p型扩散区域（16a）和高杂质浓度的p型扩散区域（16b）以与n型漏极扩散接触的方式形成 区域（9a）和n型源极扩散区域（9b），但不在n沟道MOS晶体管（18）的沟道区域中。 因此，可以在不改变传输门晶体管的阈值电压的情况下降低α粒子产生的电荷。

公开(公告)号：US4736343A

公开(公告)日：1988-04-05

申请号：US929370

申请日：1986-11-12

Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Yasuhiro Konishi

Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC: G11C11/409 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/24

CPC classification number: G11C11/4094 ,  G11C7/12

Abstract: 44Gate potentials of transistors Q.sub.R0 and Q.sub.R1 provided in an active pull-up circuit APo are always controlled to be appropriate values by a clock signal .phi..sub.p. As a result, reverse flow of electric charge from a capacitor C.sub.R0 or C.sub.R1 to a bit line LB or BL can be prevented and unfavorable influence due to such reverse flow of electric charge can be avoided in operation of the active pull-up circuit APo.

Abstract translation: 在主动上拉电路APo中提供的晶体管QR0和QR1的栅极电位总是通过时钟信号phi被控制为适当的值。 结果，可以防止从电容器CR0或CR1到位线LB或＆amp; upbar＆B的电荷的反向流动，并且在有源上拉电路APo的操作中可以避免由于这种反向电荷的不利影响 。

公开(公告)号：US4730320A

公开(公告)日：1988-03-08

申请号：US825869

申请日：1986-02-04

Applicant: Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Tsutomu Yoshihara

Inventor： Hideto Hidaka ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Katsumi Dosaka ,  Tsutomu Yoshihara

IPC: G06F11/10 ,  G06F11/267

CPC classification number: G06F11/2215 ,  G06F11/1008 ,  G06F11/1076

Abstract: A semiconductor memory device comprises a data input switching circuit (20) connected between the output side of a write check bit generating circuit (2) and the input side of a check bit memory cell array (32), a data output switching circuit (30) connected to the input side of an address decoder (9), and an address switching circuit (10) connected to the output side of the address decoder (9). When a test mode is entered, the data input switching circuit (2), data output switching circuit (30) and address switching circuit (10) connect a data input signal line (l), data output signal line (m) and address signal line (n), respectively, to the check bit memory cell array (32), enabling the check bit memory cell array (32) to be accessed from the outside.

Abstract translation: 半导体存储器件包括连接在写入校验位产生电路（2）的输出侧和校验位存储单元阵列（32）的输入侧之间的数据输入切换电路（20），数据输出切换电路（30） ）和连接到地址解码器（9）的输出侧的地址切换电路（10）。 当输入测试模式时，数据输入切换电路（2），数据输出切换电路（30）和地址切换电路（10）连接数据输入信号线（l），数据输出信号线（m）和地址信号 （n）分配给校验位存储单元阵列（32），从而能够从外部访问校验位存储单元阵列（32）。

公开(公告)号：US4694432A

公开(公告)日：1987-09-15

申请号：US709409

申请日：1985-03-06

Applicant: Hideshi Miyatake ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

Inventor： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

IPC: G11C11/401 ,  G11C8/08 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC classification number: G11C29/787 ,  G11C8/08

Abstract: A semiconductor memory device comprises a plurality of row decoder circuits connected with word lines for selecting memory cells. The row decoder circuits include normal row decoder circuits and spare row decoder circuits which can be selected in place of a normal row decoder circuit in case where a fault occurs in a memory cell selected by a word line connected to the normal row decoder circuit. An RAS signal (precharge signal) is applied to an output line (12) of a normal row decoder circuit through a precharge bus (31). A link element (11p) is inserted in the precharge bus (31). The link element (11p) is an element which can be melted by a laser beam, whereby the normal row decoder circuit associated is maintained in a non-selective state. A clamp circuit (14) is also connected to the output line (12). The clamp circuit (14) is a circuit for maintaining the output line (12) at a prescribed low level when the link element (11p) is melted and the associated decoder circuit is brought into a non-selective state.

Abstract translation: 半导体存储器件包括与用于选择存储器单元的字线连接的多个行解码器电路。 行解码器电路包括普通行解码器电路和备用行解码器电路，其可以在由连接到正常行解码器电路的字线选择的存储单元中发生故障的情况下代替普通行解码器电路。 通过预充电总线（31）将正常行解码器电路的输入线（12）上的上拉和下拉信号（预充电信号）施加到正常行解码器电路。 连接元件（11p）插入预充电总线（31）中。 连接元件（11p）是可以被激光束熔化的元件，由此相关联的正常行解码器电路保持在非选择状态。 钳位电路（14）也连接到输出线（12）。 钳位电路（14）是当连接元件（11p）熔化并且相关联的解码器电路处于非选择状态时，用于将输出线（12）保持在规定的低电平的电路。

公开(公告)号：US4641286A

公开(公告)日：1987-02-03

申请号：US581000

申请日：1984-02-16

Applicant: Kazuhiro Shimotori ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Hideshi Miyatake

Inventor： Kazuhiro Shimotori ,  Kazuyasu Fujishima ,  Hideyuki Ozaki ,  Hideshi Miyatake

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

CPC classification number: G11C29/781

Abstract: A semiconductor memory device in which at least a line decoder or a column decoder in multiplex form is provided to select one line selection signal or column selection signal. When the line decoder or column decoder is defective, or when the word line or bit line associated with the line decoder or column decoder involves a defective bit, the defective line decoder, column decoder, word line or bit line is inactivated. The inactivated line decoder or column decoder is replaced with an auxiliary line decoder or column decoder.

Abstract translation: 一种半导体存储器件，其中提供至少一个线路解码器或多路复用形式的列解码器以选择一个线选择信号或列选择信号。 当线路解码器或列解码器故障时，或者当与线路解码器或列解码器相关联的字线或位线涉及有缺陷的位时，故障线解码器，列解码器，字线或位线被停用。 灭活的行解码器或列解码器被替换为辅助线路解码器或列解码器。

公开(公告)号：US4455628A

公开(公告)日：1984-06-19

申请号：US439215

申请日：1982-11-04

Applicant: Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

Inventor： Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Kazuhiro Shimotori

IPC: G11C11/417 ,  G05F3/20 ,  G11C5/14 ,  G11C11/34 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03K19/094 ,  G11C7/00

CPC classification number: G11C5/146 ,  G05F3/205 ,  G11C11/4074

Abstract: The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits comprising capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.

Abstract translation: 本公开描述了一种衬底偏置产生电路，其中内部＆上行＆行（行地址选通）信号和内部CAS（列地址选通）信号，两者都与外部＆上行＆R信号和从外部提供的外部＆upbar＆C同步 除了自振荡器，分别激活包括电容器和整流元件的电路，以便在RAM的保持时间期间降低功率消耗，并且在其操作期间获得增加的电荷泵电流。

公开(公告)号：US5982678A

公开(公告)日：1999-11-09

申请号：US882758

申请日：1997-06-26

Applicant: Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

Inventor： Tsukasa Ooishi ,  Yoshio Matsuda ,  Kazutami Arimoto ,  Masaki Tsukude ,  Kazuyasu Fujishima

IPC: G11C11/413 ,  G11C7/00 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10

CPC classification number: G11C29/806 ,  G11C29/781 ,  G11C8/10

Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.