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    Methods of forming resistive memory devices
    31.
    发明授权
    Methods of forming resistive memory devices 有权
    形成电阻式存储器件的方法

    公开(公告)号：US08058097B2

    公开(公告)日：2011-11-15

    申请号：US12784230

    申请日：2010-05-20

    Applicant: Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    Inventor： Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    IPC: H01L21/36

    CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

    Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

    Abstract translation: 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

    RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS
    34.
    发明申请
    RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS 失效
    包括选择的参考存储器单元的电阻存储器件

    公开(公告)号：US20090067216A1

    公开(公告)日：2009-03-12

    申请号：US12265941

    申请日：2008-11-06

    Applicant: Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    Inventor： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC: G11C11/00 ,  G11C11/02 ,  G11C7/00

    CPC classification number: G11C11/1675 ,  G11C11/1673

    Abstract: A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.

    Abstract translation: 磁存储单元阵列器件可以包括在多个第一和第二存储器单元之间延伸的第一电流源线，该第一和第二存储器单元被配置用于相应的同时编程，并且被配置为进行用于写入多个第一和第二存储器单元之一的足够的编程电流，第一电流 源极晶体管，耦合到第一电流源线和字线，编程导体，其耦合到第一电流源晶体管并且延伸跨越耦合到多个第一和第二存储器单元中的一个的位线，被配置为导通编程电流 耦合到编程导体并被配置为将编程电流从编程导体切换到第二电流源晶体管输出的第二电流源晶体管，与多个第一和第二晶体管中的一个相邻延伸的第二电流源极线 与第一电流源线相对的存储单元，af 第一偏置电路，被配置为将第一偏置电压施加到在读取操作期间被选择访问的第一或第二存储器单元;以及第二偏置电路，被配置为将第二偏置电压施加到未被选择以在读取期间访问的第一或第二存储器单元 操作。

    RESISTIVE MEMORY DEVICES AND METHODS OF FORMING RESISTIVE MEMORY DEVICES
    35.
    发明申请
    RESISTIVE MEMORY DEVICES AND METHODS OF FORMING RESISTIVE MEMORY DEVICES 有权
    电阻记忆体装置及形成电阻记忆体装置的方法

    公开(公告)号：US20090065760A1

    公开(公告)日：2009-03-12

    申请号：US12207889

    申请日：2008-09-10

    Applicant: Jang Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    Inventor： Jang Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    IPC: H01L45/00 ,  H01L21/44

    CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

    Abstract: Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

    Abstract translation: 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRANSITION METAL OXIDE LAYER AND RELATED DEVICE
    36.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING TRANSITION METAL OXIDE LAYER AND RELATED DEVICE 有权
    具有过渡金属氧化物层的半导体器件的制造方法及相关器件

    公开(公告)号：US20090020745A1

    公开(公告)日：2009-01-22

    申请号：US12175602

    申请日：2008-07-18

    Applicant: Jun-Ho Jeong ,  Jang-Eun Lee ,  Se-Chung Oh ,  Kyung-Tae Nam ,  In-Gyu Baek

    Inventor： Jun-Ho Jeong ,  Jang-Eun Lee ,  Se-Chung Oh ,  Kyung-Tae Nam ,  In-Gyu Baek

    IPC: H01L21/329 ,  H01L47/00

    CPC classification number: H01L27/24 ,  G11C13/003 ,  G11C2213/76 ,  H01L27/224

    Abstract: Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer.

    Abstract translation: 提供一种具有能够防止蛇电流的开关装置的半导体器件的制造方法。 首先，将过渡金属氧化物层和泄漏控制层交替层叠在基板上1〜20次，以形成可变电阻层。 与其稳定状态相比，过渡金属氧化物层形成为含有过量的过渡金属。 泄漏控制层可以由选自Mg层，Ta层，Al层，Zr层，Hf层，多晶硅层，导电性碳基层和Nb层中的一种形成。

    Storage of non-volatile memory device and method of forming the same
    37.
    发明申请
    Storage of non-volatile memory device and method of forming the same 审中-公开
    存储非易失性存储器件及其形成方法

    公开(公告)号：US20080237693A1

    公开(公告)日：2008-10-02

    申请号：US12078255

    申请日：2008-03-28

    Applicant: Jang-Eun Lee ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Jun-Ho Jeong ,  Dae-Kyom Kim

    Inventor： Jang-Eun Lee ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Jun-Ho Jeong ,  Dae-Kyom Kim

    IPC: H01L29/788 ,  H01L21/28

    CPC classification number: H01L45/04 ,  H01L27/2418 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675

    Abstract: There is provided a storage of a non-volatile memory device and a method of forming the same. The storage of example embodiments may include a bottom electrode, a first tunneling insulating layer on the bottom electrode, a middle electrode on the first tunneling insulating layer, a second tunneling insulating layer on the middle electrode, and a top electrode on the second tunneling insulating layer. The first and second tunneling insulating layers may be formed of metal oxide having a thickness from about several Å to about several tens Å and a storage may be formed to have a width of about several tens nm. Therefore, a multi bit storage, increased integration, increased operation speed and decreased power consumption may be realized.

    Abstract translation: 提供了一种非易失性存储器件的存储器及其形成方法。 示例性实施例的存储可以包括底部电极，底部电极上的第一隧道绝缘层，第一隧道绝缘层上的中间电极，中间电极上的第二隧道绝缘层，以及第二隧道绝缘层上的顶部电极 层。 第一和第二隧道绝缘层可以由具有约几埃至约几十埃的厚度的金属氧化物形成，并且存储可以形成为具有约几十纳米的宽度。 因此，可以实现多位存储，增加的集成度，增加的操作速度和降低的功耗。

    Resistive memory devices including selected reference memory cells and methods of operating the same
    40.
    发明申请
    Resistive memory devices including selected reference memory cells and methods of operating the same 审中-公开
    电阻式存储器件包括所选择的参考存储单元及其操作方法

    公开(公告)号：US20070103964A1

    公开(公告)日：2007-05-10

    申请号：US11580766

    申请日：2006-10-13

    Applicant: Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    Inventor： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC: G11C11/00

    CPC classification number: G11C11/1675 ,  G11C11/1673

    Abstract: A method of accessing a resistive memory device can include applying a predetermined voltage level to a first word line coupled to a first resistive memory cell block during a read operation of a second resistive memory cell block coupled to a second word line, A programming current can be conducted via a pair of opposing current source transistors located on first and second opposing sides of the first block to provide the programming current from the first end to the second end across bit lines coupled to resistive memory cells in the first block and to provide the programming current parallel to the second block.

    Abstract translation: 访问电阻式存储器件的方法可以包括在耦合到第二字线的第二电阻存储器单元块的读取操作期间将预定电压电平施加到耦合到第一电阻存储器单元块的第一字线。编程电流可以 位于第一块的第一和第二相对侧上的一对相对的电流源晶体管导通，以提供编程电流，从而从第一端到第二端跨越与第一块中的电阻式存储单元耦合的位线，并提供 编程电流平行于第二块。

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