公开(公告)号：US10523352B2

公开(公告)日：2019-12-31

申请号：US15890219

申请日：2018-02-06

Applicant: Valens Semiconductor Ltd.

Inventor： Shai Stein ,  Eran Rippel

IPC: H04J3/06 ,  H04N21/43 ,  H04L12/40 ,  H03M13/11 ,  H03M13/29 ,  H04L1/00 ,  H04L1/18 ,  H04N21/4363

Abstract: Methods and systems that enable recovery of a lost packet from an incomplete block transmitted over a communication network. In one embodiment, a system includes a first processor configured to: receive a block of packets during a period spanning a certain duration, calculate a parity packet (PP) for the block, and provide in PP an indication of the number of packets in the block, where the block comprises k

公开(公告)号：US10270542B2

公开(公告)日：2019-04-23

申请号：US16142138

申请日：2018-09-26

Applicant: Valens Semiconductor Ltd.

Inventor： Eyran Lida ,  Aviv Salamon ,  Gaby Gur Cohen ,  Israel Greiss

IPC: H04B15/00 ,  H04L25/03 ,  H04B1/38

Abstract: Methods and systems for fast convergence. One embodiment includes the following steps: extracting a digital representation of a common mode signal of a received differential signal sent by a transceiver, and generating, by a fast-adaptive mode-conversion canceller (FA-MCC), a compensation signal to mitigate differential interference; feeding the received differential signal to at least one of the following: a digital equalizer, and a digital canceller (DEDC); wherein the FA-MCC and the DEDC feed a slicer; responsive to receiving an indication that a serious differential interference has occurred, indicating the transceiver to transmit known data; and utilizing the received known data for improving the accuracy of the slicer's errors, which enables rapid adaptation of the FA-MCC to a level that mitigates the serious differential interference and enables requesting retransmission of erred packets fast enough to maintain a fixed rate of data transmission over a 2-millisecond window.

公开(公告)号：US10171182B2

公开(公告)日：2019-01-01

申请号：US15169914

申请日：2016-06-01

Applicant: Valens Semiconductor Ltd.

Inventor： Eyran Lida ,  Aviv Salamon ,  Gaby Gur Cohen ,  Israel Greiss

IPC: H04B15/00 ,  H04B1/38 ,  H04L25/03

Abstract: Methods and systems for fast recovery, such as a transceiver that assists a second transceiver to recover rapidly from quality degradation. In one embodiment, the transceiver includes a receiver and a transmitter. The receiver receives from the second transceiver an indication to transmit known data, wherein utilizing the known data enables the second transceiver to recover within less than 1 millisecond from the quality degradation. And the transmitter transmits the known data, wherein the known data comprises bitwise complement code words of an idle sequence, and each bitwise complement code word appears in the idle sequence.

公开(公告)号：US20180226993A1

公开(公告)日：2018-08-09

申请号：US15890203

申请日：2018-02-06

Applicant: Valens Semiconductor Ltd.

Inventor： Shai Stein ,  Eran Rippel

IPC: H03M13/11 ,  H03M13/29

Abstract: Methods and systems that enable recovery lost packets that were transmitted over a communication network. In one embodiment, a device includes a receiver and a processor. The receiver receives n packets that belong to a set comprising n+2 packets transmitted over the communication network, where the set includes: n data packets, a row parity packet (RPP), and a diagonal parity packet (DPP). Each received packet comprises n segments. Each segment of RPP comprises a result of a parity function applied to a row parity set comprising n segments, each belonging to a different packet from among the n data packets. Each segment of DPP comprises a result of a parity function applied to a diagonal parity set comprising n segments, each belonging to a different packet selected from a group comprising the n data packets and RPP. The processor utilized the received packets to recover two lost packets.

公开(公告)号：US09998397B2

公开(公告)日：2018-06-12

申请号：US15223184

申请日：2016-07-29

Applicant: Valens Semiconductor Ltd.

Inventor： Eyran Lida ,  Nadav Banet

IPC: H04L12/927 ,  H04L12/727 ,  H04L12/911 ,  H04L12/841 ,  H04N21/00 ,  H04L29/06

CPC classification number: H04L47/805 ,  H04L41/0896 ,  H04L45/121 ,  H04L47/283 ,  H04L47/726 ,  H04L47/728 ,  H04L47/801 ,  H04L69/04 ,  H04N21/00

Abstract: Methods and systems for resource reservation networks configured to maintain low latency and latency variation of co-shared sessions. A session creation module (SCM) creates a bi-directional parent session (Sp), between first and second session partners, by: allocating co-shared network resources over a first network hop, and allocating network resources over a second network hop; wherein the network resources allocated to the Sp guarantee a maximum end-to-end latency variation (e2eLV) below 100 usec. The SCM further calculates a maximum e2eLV of a potential bi-directional derivative session (Sd) between the first session partner and a third session partner; wherein the potential Sd utilizes network resources over a third network hop and the co-shared network resources over the first network hop. And the SCM creates the Sd responsive to determining that the maximum e2eLV of the Sd being below 100 usec.

公开(公告)号：US09860606B2

公开(公告)日：2018-01-02

申请号：US14834641

申请日：2015-08-25

Applicant: Valens Semiconductor Ltd.

Inventor： Eyran Lida

IPC: H04N7/01 ,  H04N21/647 ,  H04N21/2343 ,  H04N21/24 ,  H04N21/242 ,  H04N19/42 ,  H04N19/88 ,  H04N19/186 ,  H04N19/30 ,  H04N5/44

CPC classification number: H04N21/64769 ,  H04N5/44 ,  H04N7/0102 ,  H04N7/0117 ,  H04N7/0125 ,  H04N19/186 ,  H04N19/30 ,  H04N19/42 ,  H04N19/88 ,  H04N21/234309 ,  H04N21/23439 ,  H04N21/2402 ,  H04N21/2407 ,  H04N21/242 ,  H04N21/64738

Abstract: Systems and methods for fixed delay video switching. One embodiment of the system describes a fixed delay video communication link, which includes: a real-time video encoder (RT-VE) that receives an incoming high-definition uncompressed video (HD-UV), compresses the incoming HD-UV into first or second HD compressed video, and transmits the HD compressed video over a communication link to a real-time video decoder (RT-VD). The RT-VD decompresses the HD compressed video into an outgoing HD-UV. And wherein on-the-fly switches between the first and second compression ratios, while continuing to receive the incoming HD-UV uninterruptedly, are both visually lossless and maintain the same fixed delay between corresponding pixels of the incoming HD-UV and the outgoing HD-UV.

公开(公告)号：US09722763B2

公开(公告)日：2017-08-01

申请号：US12689359

申请日：2010-01-19

Applicant: Eyran Lida ,  Nadav Banet

Inventor： Eyran Lida ,  Nadav Banet

IPC: H04L5/14 ,  H04L1/00 ,  H04L1/18 ,  H04L25/49 ,  H04L27/00

CPC classification number: H04L5/143 ,  H04L1/007 ,  H04L1/1819 ,  H04L1/1841 ,  H04L1/1887 ,  H04L25/4919 ,  H04L27/0008

Abstract: A communication link comprising: a first transceiver configured to transmit a first set of packets at a predetermined rate with a first error resistance level, store the transmitted data in a buffer, receive a retransmission request, and retransmit the relevant data using one or more packets encoded with a second error resistance level that is higher than the first error resistance level. And a second transceiver configured to receive the first set of packets, detect an erroneous packet, request retransmission of the erroneous packet, and forward the data received in the packets according to its original order approximately after a fixed delay.

公开(公告)号：US20160277127A1

公开(公告)日：2016-09-22

申请号：US15170019

申请日：2016-06-01

Applicant: Valens Semiconductor Ltd.

Inventor： Eyran Lida ,  Aviv Salamon ,  Gaby Gur Cohen ,  Israel Greiss

IPC: H04B15/00 ,  H04B1/10 ,  H04B1/38

CPC classification number: H04B15/00 ,  H04B1/1027 ,  H04B1/38 ,  H04L25/0276 ,  H04L25/03885

Abstract: Systems and methods for recovering rapidly from a mode-conversion of a common mode interference. One exemplary transceiver includes: a slicer configured to generate slicing decisions and slicing errors based on a differential signal, transmitted at a rate above 500 Mbps, which is received from a second transceiver; and a common mode sensor analog front end (CMS-AFE) configured to sense a common mode component of the differential signal. The CMS-AFE is coupled to a fast-adaptive mode-conversion canceller (FA-MCC) configured to generate a compensation signal that compensates for differential interferences that are correlated with the common mode component. Wherein, within less than 1 millisecond from an occurrence of a differential interference that causes the packet loss to exceed 10% as a result of the mode-conversion, the transceiver is configured to utilize the slicing errors to adapt the FA-MCC to a level that reduces the packet loss rate to below 1%.

Abstract translation: 从共模干扰的模式转换中快速恢复的系统和方法。 一个示例性收发器包括：限幅器，被配置为基于从第二收发器接收的以高于500Mbps的速率发送的差分信号生成限幅判定和限幅误差; 以及被配置为感测差分信号的共模分量的共模传感器模拟前端（CMS-AFE）。 CMS-AFE耦合到配置为产生补偿与共模分量相关的差分干扰的补偿信号的快速自适应模式转换消除器（FA-MCC）。 其中，在由于模式转换而导致分组丢失超过10％的差分干扰的不到1毫秒内，收发器被配置为利用限幅误差来使FA-MCC适应水平 将丢包率降低到1％以下。

公开(公告)号：US09426006B2

公开(公告)日：2016-08-23

申请号：US12185832

申请日：2008-08-05

Applicant: Eyran Lida ,  Avi Avrahami ,  Alon Benzaray ,  Nadav Banet ,  Micha Risling ,  Massad Eyal ,  Zeev Brunin

Inventor： Eyran Lida ,  Avi Avrahami ,  Alon Benzaray ,  Nadav Banet ,  Micha Risling ,  Massad Eyal ,  Zeev Brunin

IPC: H04N7/26 ,  H04L27/00

CPC classification number: H04L27/0008

Abstract: A low power partial functionality communication link that includes a first mode of operation for transmitting a first high throughput data stream including a plurality of data types over wires, and a second low power partial functionality mode of operation for transmitting, over a subset of the wires used for transmitting the first data stream, a second low throughput bidirectional data stream that may include less data types than the first data stream.

Abstract translation: 一种低功率部分功能性通信链路，其包括用于通过线路发送包括多个数据类型的第一高吞吐量数据流的第一操作模式和用于在所述线路的子集上传输的第二低功率部分功能操作模式 用于发送第一数据流，第二低通量双向数据流，其可以包括比第一数据流更少的数据类型。

公开(公告)号：US09407394B2

公开(公告)日：2016-08-02

申请号：US14483811

申请日：2014-09-11

Applicant: Valens Semiconductor Ltd.

Inventor： Eyran Lida ,  Aviv Salamon

IPC: H04L1/16 ,  H04J13/00 ,  H04L5/14 ,  H04L12/801 ,  H04L12/851

CPC classification number: H04J13/0003 ,  H04L1/0003 ,  H04L5/14 ,  H04L5/1453 ,  H04L25/4908 ,  H04L47/127 ,  H04L47/2441

Abstract: Implementing flow control without using unique symbols or designated packets, comprising: sending, from a first device to a second device, high throughput packet communication. Temporarily storing the high throughput packet communication in a buffer of the second device. Calculating, by the second device, a basic idle code word sequence known to the first device. Producing an idle sequence by replacing certain M code words of the basic idle sequence with M bitwise complement code words. Transmitting the idle sequence, wherein the M bitwise complement code words are indicative of the fullness of the buffer. Receiving the idle sequence by the first device, and determining, based on a difference between the idle sequence and the basic idle sequence, that the buffer is full or expected to get full, and thus the first device stop sending packets to the second device.