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公开(公告)号：US20240204020A1
公开(公告)日：2024-06-20
申请号：US18474201
申请日：2023-09-25
发明人： CHIEN-HUNG LIN , BAE-YINN HWANG , WEN-FU YU , WEI-LI WANG
IPC分类号： H01L27/146 , H01L31/0232
CPC分类号： H01L27/14625 , H01L27/14685 , H01L31/02327 , H01L2933/0058
摘要： An optical package structure and a method for manufacturing the same are provided. The optical package structure includes an optical element, a bonding structural member, and a light transmittable member. The bonding structural member is bonded to a surface of the optical element. The bonding structural member includes a first bonding layer, a light-absorption layer, and a second bonding layer. The first bonding layer and the second bonding layer are made of an opaque material. The light-absorption layer is disposed between the first bonding layer and the second bonding layer. The light transmittable member is bonded to the bonding structural member and spaced apart from the optical element. The light-absorption layer is configured to absorb light emitted to the bonding structural member.
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公开(公告)号：US20240136376A1
公开(公告)日：2024-04-25
申请号：US18181557
申请日：2023-03-10
发明人： DONG-RU WU , CHIEN-CHEN LEE , LI-CHUN HUNG
IPC分类号： H01L27/146 , H01L21/50
CPC分类号： H01L27/14618 , H01L21/50 , H01L24/32
摘要： A chip package structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a chip, a molding layer and a package cover. The conductive substrate has first and second board surfaces opposite to each other, and a die-bonding region is defined on the first board surface. The chip is disposed on the first board and located in the die-bonding region, and is electrically connected to the conductive substrate. The molding layer is disposed on the first board surface and surrounds the die-bonding region and the chip. The package cover is disposed on the molding layer, and the package cover, the molding layer and the conductive substrate jointly define an enclosed space surrounding the chip. Two of the conductive substrate, the molding layer and the package cover are connected to each other through a mortise-tenon joint structure.
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公开(公告)号：US20240088049A1
公开(公告)日：2024-03-14
申请号：US18510923
申请日：2023-11-16
发明人： DEI-CHENG LIU , JHIH-WEI LAI
IPC分类号： H01L23/538 , H01L23/00 , H01L23/552 , H01L25/13
CPC分类号： H01L23/5384 , H01L23/5386 , H01L23/552 , H01L24/16 , H01L25/13 , H01L2224/16227
摘要： A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a first chip, a second chip, a conductive substrate, a dielectric layer, a vertical conductive structure, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The vias penetrate through the substrate, and a part of the vias is disposed in a first die-bonding region and a second die-bonding region. The electrodes extend from the first board surface to the second board surface through the vias. The dielectric layer is formed on the substrate to cover a lower electrode portion of each of the electrodes. The vertical conductive structure is formed to be partially embedded into the dielectric layer and provide an electrical path between the first and second die-bonding regions. The dam is formed to surround the first and the second die-bonding regions.
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公开(公告)号：US20230397354A1
公开(公告)日：2023-12-07
申请号：US18113723
申请日：2023-02-24
发明人： LI-CHUN HUNG , CHIEN-CHEN LEE , CHIA-SHUAI CHANG
CPC分类号： H05K5/0247 , H05K7/1417 , G01N21/01 , H05K5/0091
摘要： A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a plurality of metal wires electrically coupling the substrate and the sensor chip, a frame fixed on the substrate, and a light-permeable layer that is disposed on the frame. The light-permeable layer has a transparent segment and a ring-shaped segment that surrounds the transparent segment. The ring-shaped segment is disposed on a top end surface of the frame, so that the light-permeable layer, the frame, and the substrate jointly define an enclosed space that accommodates the sensor chip and the metal wires therein. The ring-shaped segment has an inner ring-shaped roughened region that is arranged on an inner surface thereof and that is fixed onto the top end surface of the frame. Moreover, an inner edge of the inner ring-shaped roughened region is arranged in the enclosed space.
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公开(公告)号：US11502020B2
公开(公告)日：2022-11-15
申请号：US17039641
申请日：2020-09-30
发明人： Chia-Shuai Chang
IPC分类号： H01L23/433 , H01L25/18 , H01L23/31 , H01L23/498 , H01L23/00 , H01L27/146
摘要： An electronic device includes a chip package module which includes a chip carrier substrate, a chip, a thermal conductive unit, and an encapsulant laver. The chip is electrically connected to the chip carrier substrate. The thermal conductive unit has a first thermal conductive surface connected to the chip, and a second thermal conductive surface opposite to the first thermal conductive surface. The thermal conductive unit has a thermal conductivity greater than that of the chip. The encapsulant layer covers the chip and partially covers the thermal conductive unit in such a manner that the second thermal conductive surface is exposed from the encapsulant layer.
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公开(公告)号：US20220254826A1
公开(公告)日：2022-08-11
申请号：US17731052
申请日：2022-04-27
发明人： Chia-Shuai CHANG
IPC分类号： H01L27/146
摘要： An image sensing chip package structure includes a chip, an adhesive loop and a light-transmissible substrate member. The chip includes an image sensing region. The adhesive loop is connected to the chip, and has an inner peripheral surface that defines a plurality of protrusions which surround the image sensing region of the chip. The light-transmissible substrate member is connected to the adhesive loop oppositely of the chip to cover the image sensing region of the chip. Methods of manufacturing the image sensing chip package structures are also provided.
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公开(公告)号：US09801288B2
公开(公告)日：2017-10-24
申请号：US14700229
申请日：2015-04-30
发明人： Chien-Cheng Wei , Ta-Hsiang Chiang
CPC分类号： H05K3/4661 , H05K1/0298 , H05K1/0306 , H05K1/092 , H05K3/0091 , H05K3/244 , H05K3/46 , H05K3/4605 , H05K2201/10106
摘要： A method for manufacturing a multilayer circuit board includes: forming a first patterned conductive layer on a ceramic substrate, the first patterned conductive layer having a first circuit pattern and a first submount pattern; forming a second patterned conductive layer on the first patterned conductive layer, the second patterned conductive layer having a second circuit pattern and a second submount pattern; forming an insulating layer on the ceramic substrate; and forming a third patterned conductive layer on the insulating layer. The third patterned conductive layer having a third circuit pattern and a third submount pattern. The first, second and third submount patterns are stacked one above another.
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38.发明申请Hermetic Semiconductor Package Structure and Method for Manufacturing the same 审中-公开密封半导体封装结构及其制造方法公开(公告)号：US20130155629A1
公开(公告)日：2013-06-20
申请号：US13469052
申请日：2012-05-10
申请人： Shao-Pin Ru
发明人： Shao-Pin Ru
CPC分类号： H01L21/50 , B81B7/007 , B81B2207/096 , B81C2203/0109 , B81C2203/019 , H01L23/055 , H01L23/10 , H01L23/49827 , H01L2224/48091 , H01L2224/73265 , H01L2924/1461 , Y10T29/4913 , H01L2924/00014 , H01L2924/00
摘要： The invention provides a semiconductor package structure, comprising: a substrate having a first surface and a second surface; a first conductive layer plated on the first surface; a semiconductor element attached to the first conductive layer on the first surface of the substrate for electrically connecting; a second conductive layer plated on the first surface and surrounded the semiconductor element and the first conductive layer, wherein the height of the second conductive layer is higher than the first conductive layer; and a lid attached to the top of the second conductive layer for sealing the semiconductor element.
摘要翻译： 本发明提供一种半导体封装结构，包括：具有第一表面和第二表面的衬底; 电镀在第一表面上的第一导电层; 半导体元件，其附接到所述基板的所述第一表面上的所述第一导电层，用于电连接; 电镀在第一表面上并包围半导体元件和第一导电层的第二导电层，其中第二导电层的高度高于第一导电层; 以及附接到第二导电层的顶部用于密封半导体元件的盖。
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公开(公告)号：US5045639A
公开(公告)日：1991-09-03
申请号：US570332
申请日：1990-08-21
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L23/564 , H01L23/49827 , H01L23/49866 , H01L2924/0002 , H01L2924/09701
摘要： A pin grid array package having a substrate formed from a ceramics containing a 90% or higher alumina composition. The substrate has an palladium-silver layer on an upper surface thereof with a silver layer further provided on the Pd-Ag layer and a gold bonding pad on a outer periphery of a cavity of the substrate so as to provide electrical connection between pins and chip. The Ag layer is covered with a dielectric layer to prevent contamination from moisture.
摘要翻译： 一种具有由包含90％或更高的氧化铝组成的陶瓷形成的基板的引脚格栅阵列封装。 基板在其上表面上具有钯 - 银层，其中还设置在Pd-Ag层上的银层和在基板的空腔的外周上的金焊盘，以提供引脚和芯片之间的电连接 。 Ag层被介电层覆盖以防止水分的污染。
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公开(公告)号：US20240321810A1
公开(公告)日：2024-09-26
申请号：US18448961
申请日：2023-08-13
发明人： YU-CHIAO TSENG , CHIA-MIN WU , YI-TA LAI , CHENG-YUAN WANG , SZU-YAO HUANG
IPC分类号： H01L23/00
CPC分类号： H01L24/33 , H01L24/32 , H01L24/48 , H01L2224/32225 , H01L2224/3303 , H01L2224/3305 , H01L2224/33135 , H01L2224/33505 , H01L2224/48105 , H01L2224/48227 , H01L2924/16235 , H01L2924/1631 , H01L2924/16588 , H01L2924/182
摘要： A chip package structure includes a substrate, a chip, a light-permeable element, and an adhesive element. The chip is disposed on the substrate. The light-permeable element is disposed above the chip. The adhesive element is connected between the chip and the light-permeable element. The adhesive element surrounds the chip for formation of an accommodating space, and the chip is located in the accommodating space. The adhesive element includes two material layers having complementary visible light absorption spectra, such that the adhesive element is capable of being used to absorb full visible spectrum light.
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