公开(公告)号：US6049231A

公开(公告)日：2000-04-11

申请号：US118471

申请日：1998-07-17

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： H03K17/693 ,  H03K19/096 ,  H03K19/01 ,  H03K19/094

CPC分类号： H03K17/693

摘要： A dynamic multiplexer circuit (20) comprising an integer number N of data providing circuits (26, 28, 30), wherein the integer number N is greater than one. Each of the plurality of data providing circuits comprises a precharge node (26.sub.PN, 28.sub.PN, 30.sub.PN) to be precharged to a precharge voltage during a precharge phase, and a conditional series discharge path (26.sub.L and 26.sub.DT, 28.sub.L and 28.sub.DT, 30.sub.L and 30.sub.DT) conrected to the precharge node Each discharge path is operable in response to at least one enabling input signal (INPUTS.sub.26, INPUTS.sub.28, INPUTS.sub.30) to discharge the precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node. Each of the plurality of data providing circuits further comprises an inverter (26.sub.INV, 28.sub.INV, 30.sub.INV) coupled to the precharge node and having an output for providing a second monotonic transitioning data signal. The second monotonic transitioning data signal is complementary of the first monotonic transitioning data signal. The dynamic multiplexer further comprises the integer number N of data select paths. Each of the data select paths comprises a select transistor T1, T2, T3), the transistor having a source coupled to receive the second monotonic transitioning data signal and a gate connected to receive a select signal (SEL1, SEL2, SEL3). A drain of the select transistor in each of the data select paths is coupled to conditionally discharge an output precharge node (DSEL.sub.PN). Lastly, the dynamic multiplexer includes an output inverter (INV.sub.DOUT) having an input connected to the output precharge node. In a given evaluate phase of operation, in response to assertion of a select signal corresponding to one of the data select paths, the transistor receiving the asserted select signal at its gate and the second monotonic transitioning data signal at its source conducts for providing an output data signal at an output of the output inverter, wherein the output data signal represents three signal inversions of the at least one enabling input signal.

公开(公告)号：US5559453A

公开(公告)日：1996-09-24

申请号：US534920

申请日：1995-09-28

申请人： James J. Covino ,  Jose R. Sousa

发明人： James J. Covino ,  Jose R. Sousa

IPC分类号： H03K19/003 ,  H03K19/01

CPC分类号： H03K19/00323 ,  H03K19/003

摘要： A low power, high speed, multistage asynchronous logic circuit having an interlocked restore mechanism. A first logic circuit detects a valid input signal and drives an output to a second logic circuit. The second logic circuit receives inputs from the first logic circuit and drives a data ready signal back to the first logic circuit when it detects the output from the first logic circuit. The first logic circuit resets when it receives the data ready signal from the second logic circuit and it detects that its inputs have been reset.

摘要翻译： 具有互锁恢复机制的低功率，高速，多级异步逻辑电路。 第一逻辑电路检测有效输入信号并将输出驱动到第二逻辑电路。 当第二逻辑电路检测到来自第一逻辑电路的输出时，第二逻辑电路从第一逻辑电路接收输入并将数据就绪信号驱动回第一逻辑电路。 当第一逻辑电路从第二逻辑电路接收到数据就绪信号并且检测到其输入已被复位时复位。

公开(公告)号：US5557581A

公开(公告)日：1996-09-17

申请号：US419377

申请日：1995-04-10

申请人： Godfrey P. D'Souza

发明人： Godfrey P. D'Souza

IPC分类号： H03K19/0175 ,  G11C7/10 ,  H03K19/01 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1006

摘要： A logic and memory circuit with reduced input-to-output signal propagation delay includes signal processor and memory elements connected in parallel for performing "memory work" simultaneously with "logical work" and/or "electrical work." Incorporated within a flip-flop having master and slave latches which perform the memory work (i.e. data storage) on the input and output logic signals, respectively, is a signal processor which processes one or more input signals to provide an output signal. Where memory work and electrical work are to be performed simultaneously, the signal processor includes a serial group of circuits having successively larger transistors for buffering an input signal to provide the output signal simultaneously with the storage of the input and output signals by the master and slave latches, respectively. Where memory work and logical work are to be performed simultaneously, the signal processor includes a logic function circuit (e.g. a logic gate) for logically processing one or more input signals to provide the output signal simultaneously with the storage of the input and output signals by the master and slave latches, respectively.

摘要翻译： 具有降低的输入到输出信号传播延迟的逻辑和存储器电路包括并行连接的信号处理器和存储器元件，以与“逻辑工作”和/或“电气工作”同时执行“存储器工作”。 在具有对输入和输出逻辑信号执行存储器工作（即，数据存储））的主锁存器和从锁存器的触发器中分别是处理一个或多个输入信号以提供输出信号的信号处理器。 在同时执行存储器工作和电气工作的情况下，信号处理器包括具有连续较大晶体管的串行电路组，用于缓冲输入信号，以在由主器件和从器件同时存储输入和输出信号的同时提供输出信号 锁存器。 在存储器工作和逻辑工作要同时执行的情况下，信号处理器包括用于逻辑处理一个或多个输入信号的逻辑功能电路（例如逻辑门），以通过输入和输出信号的存储同时提供输出信号 主从锁存器。

公开(公告)号：US5442304A

公开(公告)日：1995-08-15

申请号：US137437

申请日：1993-10-15

申请人： Jack T. Wong ,  Fabiano Fontana ,  Martha Chan

发明人： Jack T. Wong ,  Fabiano Fontana ,  Martha Chan

IPC分类号： H03K19/00 ,  H03K19/017 ,  H03K19/01 ,  H03K19/0175

CPC分类号： H03K19/0013 ,  H03K19/01721

摘要： A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.

摘要翻译： 公开了一种门钳位电路，其包括逻辑门和偏置电路装置。 通过该钳位电路，在输出信号的低电平至高电平和高电平至低电平转换期间电路的运行速度得到优化，同时功耗最小化。

公开(公告)号：US5440182A

公开(公告)日：1995-08-08

申请号：US142900

申请日：1993-10-22

申请人： Ivo J. Dobbelaere

发明人： Ivo J. Dobbelaere

IPC分类号： H03K19/017 ,  H03K19/177 ,  H03K19/01

CPC分类号： H03K19/17736 ,  H03K19/01742 ,  H03K19/17704 ,  H03K19/17792

摘要： A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, is disclosed. In one embodiment, a plurality of clocked dynamic logic circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. During the precharge clock phase, the circuits precharge the intermediate nodes to a high logic level. During the evaluation clock phase, each circuit is initially in the stand-by state, in which it monitors the logic level on its network node. If a substantial deviation from the high level towards the low level is detected, the circuit switches to the discharge state, in which it enforces that level change by connecting its network node to the low level. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards a low level, and their circuits in turn switch to the discharge state. Thus, a forced high-to-low level change on a node during the evaluation clock phase quickly propagates to its connected nodes.

摘要翻译： 公开了可用于快速，区域高效的灵活可编程互连体系结构中的电路方式。 在一个实施例中，每个具有单个网络节点的多个时钟动态逻辑电路连接到可编程互连体系结构的中间节点。 在预充电时钟阶段期间，电路将中间节点预充电到高逻辑电平。 在评估时钟阶段期间，每个电路最初处于待机状态，其中它监视其网络节点上的逻辑电平。 如果检测到从高电平到低电平的显着偏差，则电路切换到放电状态，其中通过将其网络节点连接到低电平来实现该电平改变。 这导致通过导通的可编程开关连接的相邻节点上的电位变为低电平，并且它们的电路又转换到放电状态。 因此，在评估时钟阶段期间，节点上强制的高到低电平变化快速传播到其连接的节点。

公开(公告)号：US5386151A

公开(公告)日：1995-01-31

申请号：US105825

申请日：1993-08-11

申请人： Alan C. Folmsbee

发明人： Alan C. Folmsbee

IPC分类号： H01L27/04 ,  H01L21/822 ,  H02M3/07 ,  H03K3/01 ,  H03K19/01

CPC分类号： H02M3/073

摘要： A low voltage charge pump operable with a low voltage power supply and a clock signal is provided for delivering a final output voltage which is higher than the supply voltage. The low voltage charge pump comprises MOS capacitors formed of MOS devices, each capacitor including a p-well acting as a plate of the respective capacitor. Through this arrangement, the effective area of the capacitor is increased resulting in an increase in capacitance. Therefore, a more efficient charge pumping effect is provided in a low voltage power supply such as 3.3 volts. The p-well of each of the capacitor is driven from ground voltage to one threshold voltage less than the supply voltage to minimize forward bias of the p-wells and the n-type substrates of the MOS devices.

摘要翻译： 提供了可以用低电压电源和时钟信号操作的低电压电荷泵，用于传送高于电源电压的最终输出电压。 低电压电荷泵包括由MOS器件形成的MOS电容器，每个电容器包括用作相应电容器的板的p阱。 通过这种布置，电容器的有效面积增加，导致电容增加。 因此，在诸如3.3伏特的低压电源中提供更有效的电荷泵浦效应。 每个电容器的p阱从地电压驱动到小于电源电压的一个阈值电压，以最小化MOS器件的p阱和n型衬底的正向偏压。

公开(公告)号：US5332929A

公开(公告)日：1994-07-26

申请号：US55807

申请日：1993-04-08

申请人： David Chiang

发明人： David Chiang

IPC分类号： H01L21/82 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/177 ,  H03K19/01

CPC分类号： H03K19/17784 ,  H03K19/0016 ,  H03K19/018585 ,  H03K19/17704

摘要： A programmable circuit is provided with a number of current regulating circuits, such as sense amplifiers, by which the user can regulate the amount of current drawn by any of a number of circuit functions within the programmable circuit. Additional current regulating circuits are associated with circuit elements which can be programmably shared between one or more circuit functions. The user can therefore programmably control the current consumption, and thereby the speed, of each circuit function as well as circuit functions interacting via the shared circuit elements.

摘要翻译： 可编程电路设有多个电流调节电路，例如读出放大器，用户可以通过该电流调节电路调节由可编程电路内的多个电路功能中的任何一个引出的电流量。 附加的电流调节电路与可在一个或多个电路功能之间可编程共享的电路元件相关联。 因此，用户可以可编程地控制每个电路功能的电流消耗以及由此的速度，以及经由共享电路元件交互的电路功能。

公开(公告)号：US5321368A

公开(公告)日：1994-06-14

申请号：US24644

申请日：1993-03-01

申请人： Josef Hoelzle

发明人： Josef Hoelzle

IPC分类号： H03K3/037 ,  G06F1/12 ,  H03K19/01 ,  H03K19/20 ,  H04L7/00

CPC分类号： H03K19/01

摘要： A synchronized, digital sequential circuit includes state-controlled memory elements, each having a clock input, at least two outputs being complementary to one another and at least two inputs, which are connected to a logical OR linkage or wired OR connection. At least two state-controlled memory elements are connected in series. A first memory element performs the OR linkage or operation and a second memory element performs the AND linkage or operation of a combinatorial logic function. The settling time of a memory element and the delay time for forming the OR and AND linkages or operations coincide. Therefore, a high speed of operation is possible in the sequential circuit.

摘要翻译： 同步的数字顺序电路包括状态控制的存储器元件，每个具有时钟输入，至少两个输出彼此互补，至少两个输入连接到逻辑或链接或有线OR连接。 至少两个状态控制的存储器元件串联连接。 第一存储器元件执行OR链接或操作，并且第二存储器元件执行组合逻辑功能的AND联动或操作。 存储元件的建立时间和形成OR和AND链接或操作的延迟时间重合。 因此，在顺序电路中可以实现高速运行。

公开(公告)号：US5270592A

公开(公告)日：1993-12-14

申请号：US933345

申请日：1992-08-21

申请人： Tadao Takahashi ,  Ichiro Yamamoto ,  Hiroyuki Fukuyama

发明人： Tadao Takahashi ,  Ichiro Yamamoto ,  Hiroyuki Fukuyama

IPC分类号： H01L21/82 ,  G06F1/10 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H03K19/00 ,  H03K21/02 ,  H03K19/01 ,  H03K5/13

CPC分类号： H01L23/5222 ,  G06F1/10 ,  H01L2924/0002

摘要： A clock supply circuit having a circuit area includes an input terminal for receiving a clock pulse and a buffer having an input electrically connected to the input terminal and an output. The buffer is disposed in the center of the circuit area. The clock supply circuit also includes a main conductive pattern electrically connected to the output of the buffer. The main conductive pattern is disposed through the center of the circuit area. Each of the branch conductive patterns is electrically connected to the main conductive pattern and extends from the main conductive pattern. Also, each of the branch conductive patterns has a width smaller than the width of the main conductive pattern. Each of the clock receiving circuits is electrically connected to one of the branch conductive patterns and disposed in the circuit area. The number of the clock receiving circuits electrically connected to one branch conductive pattern is same.

摘要翻译： 具有电路区域的时钟供给电路包括用于接收时钟脉冲的输入端子和具有电连接到输入端子的输入端和输出端的缓冲器。 缓冲器设置在电路区域的中心。 时钟供给电路还包括电连接到缓冲器的输出的主导电图案。 主导电图案通过电路区域的中心布置。 每个分支导电图案电连接到主导电图案并且从主导电图案延伸。 此外，每个分支导电图案的宽度小于主导电图案的宽度。 每个时钟接收电路电连接到一个分支导电图案并且设置在电路区域中。 电连接到一个分支导电图案的时钟接收电路的数量相同。

公开(公告)号：US5270589A

公开(公告)日：1993-12-14

申请号：US821368

申请日：1992-01-16

申请人： Kazuhiro Sawada ,  Shigeru Tanaka

发明人： Kazuhiro Sawada ,  Shigeru Tanaka

IPC分类号： H03K19/0175 ,  G11C11/407 ,  G11C11/409 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/092 ,  H03K19/01

CPC分类号： H03K19/00315 ,  H01L27/092 ,  H03K19/018521

摘要： This invention provides an input/output buffer circuit which allows input/output interfacing with another device designed to output a signal having a voltage level higher than that of the supply voltage of the semiconductor integrated circuit, and prevents the formation of an input leakage current path. An NMOS transistor is inserted between the input/output pad of the semiconductor integrated circuit and the output node of an output buffer circuit. The input node of an input buffer circuit is directly connected to the output node of the output buffer circuit or is connected to the input/output pad through another) NMOS transistor. If a transistor having a low threshold value is used as this NMOS transistor, a potential having the same level as that of the supply potential is applied to its gate. If a transistor is used, a potential having a level higher than the supply potential is applied to its gate.

摘要翻译： 本发明提供了一种输入/输出缓冲电路，其允许输入/输出与设计成输出具有高于半导体集成电路的电源电压的电压的信号的设备的接口，并且防止形成输入漏电流路径 。 NMOS晶体管插入在半导体集成电路的输入/输出焊盘和输出缓冲电路的输出节点之间。 输入缓冲电路的输入节点直接连接到输出缓冲电路的输出节点，或通过另一个NMOS晶体管连接到输入/输出焊盘。 如果使用具有低阈值的晶体管作为该NMOS晶体管，则将与电源电位相同电位的电位施加到其栅极。 如果使用晶体管，则将具有高于电源电位的电平的电位施加到其栅极。