公开(公告)号：US08125810B2

公开(公告)日：2012-02-28

申请号：US12111350

申请日：2008-04-29

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： G11C19/00

CPC分类号： G11C15/04

摘要： An integrated circuit (200) includes a semiconductor memory device (202) operative for determining match between received search data and stored data in a plurality of ternary content addressable memory (TCAM) bitcells (100). The plurality of TCAM bitcells (100) each include bit storage including a pair of memory cells (102-0, 102-1) for holding stored data. The TCAM bitcells (100) also include bit comparison circuitry (104) operative for comparing between the stored data and search data on a search line coupled to the TCAM bitcell, wherein the bit comparison circuitry includes a static logic gate operable to provide a match output signal exclusive of a pulsed input. Match circuitry (205) is coupled to receive the match output signal (108) from the plurality of TCAM bitcells (100) for determining whether a match is present for a given search word.

摘要翻译： 集成电路（200）包括半导体存储器件（202），用于确定在多个三元内容可寻址存储器（TCAM）位单元（100）中的所接收的检索数据与存储的数据之间的匹配。 多个TCAM位单元（100）各自包括位存储器，其包括用于保存存储的数据的一对存储单元（102-0,102-1）。 TCAM比特单元（100）还包括比特比较电路（104），用于比较存储的数据和耦合到TCAM比特单元的搜索线上的搜索数据，其中比特比较电路包括可操作以提供匹配输出的静态逻辑门 信号不包括脉冲输入。 耦合电路（205）被耦合以从多个TCAM比特单元（100）接收匹配输出信号（108），用于确定给定搜索词是否存在匹配。

公开(公告)号：US07859024B2

公开(公告)日：2010-12-28

申请号：US12722677

申请日：2010-03-12

申请人： Patrick W Bosshart

发明人： Patrick W Bosshart

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  H01L27/0629 ,  H01L27/0811

摘要： An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at least a first row (610) and a second row (615) immediately above the first row. The first row (610) include at least a first decap filler cell (602) including a first active area (612) and a field dielectric outside the first active area (612) having a portion with a full field dielectric thickness portion 621 and a portion with a thinned field dielectric (622), and at least a first MOS transistor (618) having a gate electrode (619) on a thick gate dielectric (613) on the first active area (612) connected as a decoupling capacitor. The second row (615) includes a second decap filler cell (601) including an active area (632) and a field dielectric portion (621) and thinned field dielectric portion (622), at least a second MOS transistor (638) having a gate electrode (639) on the thick gate dielectric (613) on the second active area (632) connected as a decoupling capacitor. The thinned field dielectric (622) extends from the first decap filler cell (602) to the second decap filler cell (601) across a border (608) between the first and second decap filler cell. A method of forming an integrated circuit including high efficiency decap filler cells includes the step of gap filling a thick gate dielectric mask.

摘要翻译： 集成电路包括具有半导体表面（605）和布置成多行的多个标准单元的衬底，所述多个行包括紧邻第一行上方的至少第一行（610）和第二行（615）。 第一行（610）至少包括第一分解填充单元（602），其包括第一有源区域（612）和位于第一有源区域（612）外部的场电介质，该第一有源区域具有具有全场介质厚度部分621的部分， 具有薄场电介质（622）的部分，以及在作为去耦电容器连接的第一有源区（612）上的厚栅电介质（613）上具有栅电极（619）的至少第一MOS晶体管（618）。 第二排（615）包括包括有源区域（632）和场介电部分（621）和变稀场电介质部分（622）的第二分解填充单元（601），至少第二MOS晶体管（638）具有 位于作为去耦电容器连接的第二有源区（632）上的厚栅电介质（613）上的栅电极（639）。 稀化场介质（622）通过第一和第二拆包填充单元之间的边界（608）从第一拆包填充单元（602）延伸到第二拆包填充单元（601）。 形成包括高效率分解填充单元的集成电路的方法包括间隙填充厚栅介质掩模的步骤。

公开(公告)号：US07062635B2

公开(公告)日：2006-06-13

申请号：US10224154

申请日：2002-08-20

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： G06F3/00

CPC分类号： G06F9/3001 ,  G06F7/575 ,  G06F9/3828 ,  G06F9/3893

摘要： A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (541, 542, 543), wherein S is greater than one. Each of the sub-units is operable to execute, during an execution cycle, at least one of the instructions in the instruction set in response to at least two data arguments (A, B). The processor further comprises circuitry (58A1, 58A2, 58A3, 58B1, 58B2) for providing an updated value of the at least two data arguments to less than all S of the sub-units for a single execution cycle.

摘要翻译： 响应于包括多个指令的指令集可操作的处理器（50）。 处理器包括功能单元（52），其包括整数S的子单元（54 <1>，54> 2，54 3）， 其中S大于1。 每个子单元可操作以在执行周期期间响应于至少两个数据自变量（A，B）执行指令集中的至少一个指令。 处理器还包括电路（58A1A，58A2A，58A3，58B1，...，58A， 用于将单个执行周期的所述至少两个数据自变量的更新值提供给小于全部S个子单元。

公开(公告)号：US06366941B1

公开(公告)日：2002-04-02

申请号：US09045000

申请日：1998-03-20

申请人： Tod D. Wolf ,  Patrick W. Bosshart ,  David R. Shoemaker

发明人： Tod D. Wolf ,  Patrick W. Bosshart ,  David R. Shoemaker

IPC分类号： G06F700

CPC分类号： G06F7/724

摘要： An implementation of a multi-dimensional galois field multiplier and a method of galois field multi-dimensional multiplication which are able to support many communication standards having various symbol sizes(16), different GFs(14), and different primitive polynomials(12), in a cost-efficient manner is disclosed. The key to allow a single implementation to perform for all different GF sizes is to shift the one of the two operands(16) and primitive polynomial(12) to the left and to shift the intermediate output ZO(28) to the right in dependence upon the relative size of the GF(14) as compared to the size of the operand, primitive polynomial or intermediate output, whichever is being shifted. The shifting of the above-mentioned signals allows the MULT-XOR arrays(26) to operate on all fields with the exact same hardware with a minimum delay of 2 gates per block or with a critical delay of 2 XOR gates.

摘要翻译： 能够支持具有各种符号大小（16），不同GF（14）和不同原始多项式（12）的许多通信标准的多维伽罗瓦域乘法器和伽罗瓦域多维乘法的方法的实现， 以成本有效的方式公开。 允许单个实现对于所有不同的GF大小执行的关键是将两个操作数（16）和原始多项式（12）中的一个向左移动，并将依赖于中间输出ZO（28）向右移位 与GF（14）的相对大小相比，操作数的大小，原始多项式或中间输出（以较大者为准）。 上述信号的移位允许MULT-XOR阵列（26）在具有完全相同的硬件的所有场上操作，每个块具有2个门的最小延迟或具有2个XOR门的临界延迟。

公开(公告)号：US06279077B1

公开(公告)日：2001-08-21

申请号：US08821874

申请日：1997-03-21

申请人： Mitra Nasserbakht ,  Patrick W. Bosshart

发明人： Mitra Nasserbakht ,  Patrick W. Bosshart

IPC分类号： G06F1208

CPC分类号： G06F12/0859 ,  G06F12/0804

摘要： A microprocessor (5) including a plurality of write buffers (30) of varying sizes is disclosed. The varying sizes of the write buffers (30) allow for each write transaction from the core of the microprocessor (5) to be assigned to the most efficient write buffer size. Each write buffer (30) also includes sequential control logic (50) that issues a status code indicating the extent to which its write buffer (30) is filled; the control logic (50) advances to a more full state responsive to receiving a new data transaction from the internal bus, and advances to a more empty state responsive to completing a write transaction to the external bus. Each write buffer (30) communicates data from an internal bus (PBUS) to an external bus (BBUS) in a manner that is synchronized in the control path, rather than in the data path. Clock domain translation circuitry (65) is included within timing control circuitry (62) to translate the control signal from one clock domain to another, thus ensuring that overlapping writes do not occur. Internal snoop control circuitry (71) is also provided, for controlling access to the write buffers (30) so that memory reads missing in on-chip cache may be performed to the write buffers (30), rather than to main memory (21), if the data remains resident therein. A read buffer (33) is also disclosed, and has a plurality of entries for receiving blocks of data from the external bus (BBUS); upon receipt of a block of data, the read buffer (33) indicates the presence of data therein to the core of the microprocessor (5) to initiate its retrieval for execution of an instruction.

摘要翻译： 公开了一种包括多个不同大小的写入缓冲器（30）的微处理器（5）。 写入缓冲器（30）的不同大小允许将来自微处理器（5）的核心的每个写事务分配给最有效的写入缓冲器大小。 每个写缓冲器（30）还包括顺序控制逻辑（50），其发出指示其写缓冲器（30）被填充的程度的状态码; 所述控制逻辑（50）响应于从所述内部总线接收到新的数据事务而进入更全状态，并且响应于完成对所述外部总线的写入事务而进入更空的状态。 每个写入缓冲器（30）以在控制路径中而不是数据路径中同步的方式将数据从内部总线（PBUS）传送到外部总线（BBUS）。 时钟域转换电路（65）包括在定时控制电路（62）内，以将控制信号从一个时钟域转换到另一个时钟域，从而确保不发生重叠写入。 还提供了内部窥探控制电路（71），用于控制对写入缓冲器（30）的访问，使得可以对写入缓冲器（30）而不是主存储器（21）执行片上高速缓存中缺少的存储器读取， 如果数据保留在其中。 还公开了读缓冲器（33），并且具有用于从外部总线（BBUS）接收数据块的多个条目; 读取缓冲器（33）在接收到数据块之后，指示其中的数据存在于微处理器（5）的核心以启动其检索以执行指令。

公开(公告)号：US06246266B1

公开(公告)日：2001-06-12

申请号：US09405918

申请日：1999-09-24

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A dynamic logic circuit (16) operable in an active mode and in a power down mode, where the active mode comprises a precharge phase and an evaluate phase. The dynamic logic circuit comprises a precharge node (18PN) coupled to be precharged to a precharge voltage (VDD) during the precharge phase and operable to be discharged during the evaluate phase. The dynamic logic circuit further comprises a conditional series discharge path connected to the precharge node and comprising a plurality of transistors (18L, 18DT, 20SDVN) operable to conditionally couple the precharge node to a voltage different than the precharge voltage. Further, the dynamic logic circuit comprises an output inverter (18INV) having an input connected to the precharge node and comprising a plurality of transistors (18INVP, 18INVN) for providing an output signal representative of a voltage at the precharge node during the evaluate phase. Still further, the dynamic logic circuit comprises a precharge transistor (18PT) operable to be enabled during the power down mode and having a source/drain conductive path for coupling the precharge voltage to the precharge node during the precharge phase.

摘要翻译： 一种动态逻辑电路（16），其可在主动模式和功率下降模式下操作，其中所述主动模式包括预充电阶段和评估阶段。 动态逻辑电路包括预充电节点（18PN），其在预充电阶段期间被耦合以预充电到预充电电压（VDD），并且可以在评估阶段期间被放电。 动态逻辑电路还包括连接到预充电节点并包括多个晶体管（18L，18DT，20SDVN）的条件串联放电路径，其可操作以有条件地将预充电节点耦合到不同于预充电电压的电压。 此外，动态逻辑电路包括具有连接到预充电节点并且包括多个晶体管（18INVP，18INVN）的输入反相器（18INV），用于在评估阶段期间提供表示预充电节点处的电压的输出信号。 此外，动态逻辑电路包括可在掉电模式期间使能的预充电晶体管（18PT），并且具有用于在预充电阶段期间将预充电电压耦合到预充电节点的源极/漏极导电路径。

公开(公告)号：US6040716A

公开(公告)日：2000-03-21

申请号：US75056

申请日：1998-05-08

申请人： Patrick W. Bosshart

发明人： Patrick W. Bosshart

IPC分类号： H03K19/096 ,  H03K19/01 ,  H03K19/094

CPC分类号： H03K19/0963

摘要： A logic circuit (18) comprising a first phase domino logic circuit (20) and a second phase domino logic circuit (22). Each of the domino logic circuits comprises a precharge node (20.sub.PN, 22.sub.PN), a coupling device (20.sub.PT, 22.sub.PT) which when conducting couples the precharge node to a precharge voltage (V.sub.DD) during a precharge phase, and a discharge path (20.sub.L and 20.sub.DT, 22.sub.L and 22.sub.DT) connected to the precharge node which when conducting couples the precharge node to a voltage different than the precharge voltage during an evaluate phase. Further, each of the domino logic circuits comprises an inverter (20.sub.IN, 22.sub.IN) coupled to the precharge node and providing an output responsive to a voltage at the precharge node. The output of the inverter of the first phase domino logic circuit is connected to control the conduction of the discharge path of the second phase domino logic circuit. The logic circuit further comprises a conductor for providing a clock signal (CLOCK), and circuitry for commencing the evaluate phase of the first phase domino logic circuit at a first time (t1) in response to the clock signal transitioning from a first state to a second state. Still further, the logic circuit comprises circuitry for commencing the evaluate phase of the second phase domino logic circuit at a second time (t2) following the first time, and circuitry (26, 28) for commencing the precharge phase of the first phase domino logic circuit at a third time (t2.sub.b) following the second time. The third time corresponds to the latest of a plurality of events. A first of the plurality of events is the clock signal transitioning from the second state to the first state. A second of the plurality of events is the discharge path of the second phase domino logic circuit having sufficient time following a beginning of the evaluate phase of the second domino logic circuit to conduct to cause the voltage at the precharge node of the second phase domino logic circuit to transition to a level sufficient to trigger the output of the inverter of the second phase domino logic circuit.

公开(公告)号：US4980860A

公开(公告)日：1990-12-25

申请号：US521000

申请日：1990-05-08

申请人： Theodore W. Houston ,  Patrick W. Bosshart

发明人： Theodore W. Houston ,  Patrick W. Bosshart

IPC分类号： G11C7/12 ,  G11C7/18

CPC分类号： G11C7/12 ,  G11C7/18

摘要： A criss-crossed complementary bit line and cross-coupled pull-up means is disclosed. One bit line (26) is crossed with respect to another bit line (28) of a complementary bit line pair to reduce the effect of noise interference induced therein. P-channel cross-coupled pull-up transistors (154, 156) are connected between the bit lines (26, 28) at an intersection (148) to assure that when one bit line is pulled low by the readout of a memory cell (158), the other bit line is pulled to the supply voltage.

摘要翻译： 公开了十字交叉的互补位线和交叉耦合上拉装置。 一个位线（26）相对于互补位线对的另一个位线（28）交叉，以减少在其中引起的噪声干扰的影响。 P沟道交叉耦合上拉晶体管（154,156）在交叉点（148）处连接在位线（26,28）之间，以确保当通过存储单元的读出将一个位线拉低时 158），另一个位线被拉到电源电压。

公开(公告)号：US08050903B1

公开(公告)日：2011-11-01

申请号：US08112906

申请日：1993-08-26

申请人： Patrick W. Bosshart ,  Derek James Smith ,  Daniel Charles Pickens ,  Douglas J. Matzke

发明人： Patrick W. Bosshart ,  Derek James Smith ,  Daniel Charles Pickens ,  Douglas J. Matzke

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Apparatus for storing all logic simulation signal values generated by a logic simulator during a simulation run is provided. The apparatus includes a runtime array for storing a plurality of signal values for each time instance in a predetermined time period, and a checkpoint cache for selectively storing the plurality of signal values stored in the runtime array at selected time instances. A hyper-checkpoint array is further provided to checkpoint the signal values in the checkpoint cache. In addition, the time instances and values of memory writes are also checkpointed. A user may retrieve the value of any signal values generated during the simulation run and may additionally rewind the simulator to a user-specified time in the simulation run.

摘要翻译： 提供了用于存储在仿真运行期间由逻辑模拟器产生的所有逻辑模拟信号值的装置。 该装置包括用于在预定时间段内存储每个时间实例的多个信号值的运行时阵列和用于在所选择的时间实例中有选择地存储存储在运行时间阵列中的多个信号值的检查点高速缓存。 还提供超检查点阵列来检查检查点高速缓存中的信号值。 此外，存储器写入的时间实例和值也是检查点。 用户可以检索在仿真运行期间生成的任何信号值的值，并且可以在模拟运行中将模拟器另外倒回到用户指定的时间。

公开(公告)号：US20100163948A1

公开(公告)日：2010-07-01

申请号：US12722677

申请日：2010-03-12

申请人： Patrick W. BOSSHART

发明人： Patrick W. BOSSHART

IPC分类号： H01L27/06 ,  H01L21/31

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  H01L27/0629 ,  H01L27/0811

摘要： An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at least a first row (610) and a second row (615) immediately above the first row. The first row (610) include at least a first decap filler cell (602) including a first active area (612) and a field dielectric outside the first active area (612) having a portion with a full field dielectric thickness portion 621 and a portion with a thinned field dielectric (622), and at least a first MOS transistor (618) having a gate electrode (619) on a thick gate dielectric (613) on the first active area (612) connected as a decoupling capacitor. The second row (615) includes a second decap filler cell (601) including an active area (632) and a field dielectric portion (621) and thinned field dielectric portion (622), at least a second MOS transistor (638) having a gate electrode (639) on the thick gate dielectric (613) on the second active area (632) connected as a decoupling capacitor. The thinned field dielectric (622) extends from the first decap filler cell (602) to the second decap filler cell (601) across a border (608) between the first and second decap filler cell. A method of forming an integrated circuit including high efficiency decap filler cells includes the step of gap filling a thick gate dielectric mask.

摘要翻译： 集成电路包括具有半导体表面（605）和布置成多行的多个标准单元的衬底，所述多个行包括紧邻第一行上方的至少第一行（610）和第二行（615）。 第一行（610）至少包括第一分解填充单元（602），其包括第一有源区域（612）和位于第一有源区域（612）外部的场电介质，该第一有源区域具有具有全场介质厚度部分621的部分， 具有薄场电介质（622）的部分，以及在作为去耦电容器连接的第一有源区（612）上的厚栅电介质（613）上具有栅电极（619）的至少第一MOS晶体管（618）。 第二排（615）包括包括有源区域（632）和场介电部分（621）和变稀场电介质部分（622）的第二分解填充单元（601），至少第二MOS晶体管（638）具有 位于作为去耦电容器连接的第二有源区（632）上的厚栅电介质（613）上的栅电极（639）。 稀化场介质（622）通过第一和第二拆包填充单元之间的边界（608）从第一拆包填充单元（602）延伸到第二拆包填充单元（601）。 形成包括高效率分解填充单元的集成电路的方法包括间隙填充厚栅介质掩模的步骤。