公开(公告)号：US08199548B2

公开(公告)日：2012-06-12

申请号：US12724441

申请日：2010-03-16

申请人： Hiroyuki Fukuyama

发明人： Hiroyuki Fukuyama

IPC分类号： G11C5/02

CPC分类号： G11C8/18 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1051

摘要： A semiconductor storage device is configured to reduce data read time. In the semiconductor storage device, an input/output control circuit is formed along one side of a memory cell array disposed between a data input pad and a data output pad. The input/output control circuit is disposed between a hold command input pad and a clock input pad. Accordingly, it is possible to minimize the distances of the wirings from the input/output control circuit to the pads and to make the distances of the wirings equal and thus to minimize the read time of the memory cell array. In addition, since it is also possible to make equal wiring distances from the input/output control circuit to the address decoder and output multiplexer, it is possible to minimize the read time of the memory cell array.

摘要翻译： 半导体存储装置被配置为减少数据读取时间。 在半导体存储装置中，沿着设置在数据输入焊盘和数据输出焊盘之间的存储单元阵列的一侧形成输入/输出控制电路。 输入/输出控制电路设置在保持命令输入板和时钟输入板之间。 因此，可以使配线从输入/输出控制电路到焊盘的距离最小化，并使布线的距离相等，从而最小化存储单元阵列的读取时间。 此外，由于也可以从输入/输出控制电路到地址解码器和输出多路复用器的布线距离相等，所以可以最小化存储单元阵列的读取时间。

公开(公告)号：US20100238694A1

公开(公告)日：2010-09-23

申请号：US12724441

申请日：2010-03-16

申请人： Hiroyuki Fukuyama

发明人： Hiroyuki Fukuyama

IPC分类号： G11C5/02 ,  G11C8/10

CPC分类号： G11C8/18 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1051

摘要： A semiconductor storage device is configured to reduce data read time. In the semiconductor storage device, an input/output control circuit is formed along one side of a memory cell array disposed between a data input pad and a data output pad. The input/output control circuit is disposed between a hold command input pad and a clock input pad. Accordingly, it is possible to minimize the distances of the wirings from the input/output control circuit to the pads and to make the distances of the wirings equal and thus to minimize the read time of the memory cell array. In addition, since it is also possible to make equal wiring distances from the input/output control circuit to the address decoder and output multiplexer, it is possible to minimize the read time of the memory cell array.

摘要翻译： 半导体存储装置被配置为减少数据读取时间。 在半导体存储装置中，沿着设置在数据输入焊盘和数据输出焊盘之间的存储单元阵列的一侧形成输入/输出控制电路。 输入/输出控制电路设置在保持命令输入板和时钟输入板之间。 因此，可以使配线从输入/输出控制电路到焊盘的距离最小化，并使布线的距离相等，从而最小化存储单元阵列的读取时间。 此外，由于也可以从输入/输出控制电路到地址解码器和输出多路复用器的布线距离相等，所以可以最小化存储单元阵列的读取时间。

公开(公告)号：US20070138710A1

公开(公告)日：2007-06-21

申请号：US10589092

申请日：2005-02-07

申请人： Hiroyuki Fukuyama ,  Takehiko Yoneda ,  Shigo Kikutani

发明人： Hiroyuki Fukuyama ,  Takehiko Yoneda ,  Shigo Kikutani

IPC分类号： C04B33/32 ,  B32B9/00 ,  B32B19/00

CPC分类号： H01L35/34 ,  C04B41/009 ,  C04B41/52 ,  C04B41/90 ,  C04B2111/00844 ,  H01L35/32 ,  C04B41/0072 ,  C04B41/4519 ,  C04B41/4556 ,  C04B41/5031 ,  C04B41/51 ,  C04B35/581

摘要： [PROBLEMS] To provide a metallized non-oxide ceramic shaped article having high adhesive strength between a metal layer and a substrate and the adhesion durability and to provide a process for producing the same. [MEANS FOR SOLVING PROBLEMS] The process for producing a metallized shaped article includes: a heating step of heating a non-oxide ceramic shaped article to a temperature at or above a temperature, which is 300° C. below the oxidation start temperature of the non-oxide ceramics, without substantial dissolution of oxygen in a solid solution form during heating; an oxidation step of bringing the non-oxide ceramic substrate heated in the heating step into contact with an oxidizing gas and then holding the non-oxide ceramic substrate at a temperature above the oxidation start temperature of the non-oxide ceramics to oxidize the surface of the non-oxide ceramic shaped article and thus to form an oxide layer on the surface of the non-oxide ceramic substrate; and a metallization step of forming a metal layer on the surface of the oxide layer in the non-oxide ceramic shaped article having an oxide layer on its surface produced in the oxidation step.

摘要翻译： 本发明提供一种在金属层和基材之间具有高粘合强度的金属化非氧化物陶瓷成型制品和粘合耐久性，并提供其制造方法。 用于解决问题的方法金属化成型制品的制造方法包括：将非氧化物陶瓷成型制品加热至等于或高于低于氧化物的氧化开始温度300℃的温度的加热步骤 非氧化物陶瓷，在加热期间没有固体溶液形式的氧的实质溶解; 使在加热步骤中加热的非氧化物陶瓷基板与氧化气体接触，然后将非氧化物陶瓷基板保持在高于非氧化物陶瓷的氧化开始温度的温度下氧化表面的氧化步骤 非氧化物陶瓷成形体，从而在非氧化物陶瓷基板的表面形成氧化物层; 以及金属化工序，在氧化工序中产生的表面上形成氧化物层的非氧化物陶瓷成形体的氧化物层的表面形成金属层。

公开(公告)号：US20050034021A1

公开(公告)日：2005-02-10

申请号：US10937607

申请日：2004-09-10

申请人： Hiroyuki Fukuyama

发明人： Hiroyuki Fukuyama

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/16 ,  G11C29/46 ,  H02H3/05

CPC分类号： G11C29/46 ,  G01R31/318558 ,  G01R31/318563 ,  G11C16/04 ,  G11C29/16 ,  G11C2207/104

摘要： A semiconductor device, according to the present invention, includes an external input terminal to which first and second input test signals are supplied; a memory circuit, in which a test operation is performed in accordance with the first input test signal to provide a first test result signal; a logic circuit, in which a test operation is performed in accordance with the second input test signal to provide a second test result signal; an external output terminal from which the first and second test result signals are outputted selectively; and a switch circuit which selectively couples the memory circuit and the logic circuit to the external input terminal and the external output terminal.

摘要翻译： 根据本发明的半导体器件包括提供第一和第二输入测试信号的外部输入端子; 存储电路，其中根据第一输入测试信号执行测试操作以提供第一测试结果信号; 逻辑电路，其中根据第二输入测试信号执行测试操作以提供第二测试结果信号; 选择性地输出第一和第二测试结果信号的外部输出端子; 以及将存储电路和逻辑电路选择性地耦合到外部输入端子和外部输出端子的开关电路。

公开(公告)号：US06826101B2

公开(公告)日：2004-11-30

申请号：US10446077

申请日：2003-05-28

申请人： Hiroyuki Fukuyama

发明人： Hiroyuki Fukuyama

IPC分类号： G11C700

CPC分类号： G11C29/46 ,  G01R31/318558 ,  G01R31/318563 ,  G11C16/04 ,  G11C29/16 ,  G11C2207/104

摘要： A semiconductor device, according to the present invention, includes an external input terminal to which first and second input test signals are supplied; a memory circuit, in which a test operation is performed in accordance with the first input test signal to provide a first test result signal; a logic circuit, in which a test operation is performed in accordance with the second input test signal to provide a second test result signal; an external output terminal from which the first and second test result signals are outputted selectively; and a switch circuit which selectively couples the memory circuit and the logic circuit to the external input terminal and the external output terminal.

摘要翻译： 根据本发明的半导体器件包括提供第一和第二输入测试信号的外部输入端子; 存储电路，其中根据第一输入测试信号执行测试操作以提供第一测试结果信号; 逻辑电路，其中根据第二输入测试信号执行测试操作以提供第二测试结果信号; 选择性地输出第一和第二测试结果信号的外部输出端子; 以及将存储电路和逻辑电路选择性地耦合到外部输入端子和外部输出端子的开关电路。

公开(公告)号：US08735905B2

公开(公告)日：2014-05-27

申请号：US13809261

申请日：2011-07-14

申请人： Hiroyuki Fukuyama ,  Masayoshi Adachi ,  Akikazu Tanaka ,  Kazuo Maeda

发明人： Hiroyuki Fukuyama ,  Masayoshi Adachi ,  Akikazu Tanaka ,  Kazuo Maeda

IPC分类号： H01L29/15 ,  H01L31/0256

CPC分类号： C30B19/12 ,  C30B9/06 ,  C30B9/10 ,  C30B19/04 ,  C30B29/403 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02625 ,  H01L33/007 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a method for producing inexpensive and high-quality aluminum nitride crystals. Gas containing N atoms is introduced into a melt of a Ga—Al alloy, whereby aluminum nitride crystals are made to epitaxially grow on a seed crystal substrate in the melt of the Ga—Al alloy. A growth temperature of aluminum nitride crystals is set at not less than 1000 degrees C. and not more than 1500 degrees C., thereby allowing GaN to be decomposed into Ga metal and nitrogen gas.

摘要翻译： 提供了一种制造廉价且高品质的氮化铝晶体的方法。 含有N原子的气体被引入Ga-Al合金的熔体中，由此使氮化铝晶体在Ga-Al合金的熔体中的晶种基板上外延生长。 氮化铝晶体的生长温度设定为1000℃以上且1500℃以下，从而使GaN分解为Ga金属和氮气。

公开(公告)号：US20140097901A1

公开(公告)日：2014-04-10

申请号：US14114519

申请日：2012-06-29

申请人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Makoto Nakamura ,  Hideyuki Nosaka ,  Miwa Mutoh ,  Koichi Murata

发明人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Makoto Nakamura ,  Hideyuki Nosaka ,  Miwa Mutoh ,  Koichi Murata

IPC分类号： H03G3/30

CPC分类号： H03G3/30 ,  H03G3/3084

摘要： An automatic gain control circuit (5a) includes a peak detector circuit (10) that detects the peak voltage of the output signal from a variable gain amplifier (3), an average value detection and output amplitude setting circuit (11) that detects the average voltage of the output signals from the variable gain amplifier (3) and adds a voltage ½ the desired output amplitude of the variable gain amplifier (3) to the average voltage, and a high gain amplifier (12) that amplifies the difference between the output voltage of the peak detector circuit (10) and the output voltage of the average value detection and output amplitude setting circuit (11) and controls the gain of the variable gain amplifier (3) using the amplification result as a gain control signal. The peak detector circuit (10) includes transistors (Q1, Q2, Q3), a current source (I1), and a filter circuit. The filter circuit includes a series connection of a resistor (Ra) and a capacitor (C1).

摘要翻译： 自动增益控制电路（5a）包括检测来自可变增益放大器（3）的输出信号的峰值电压的峰值检测电路（10），检测平均值的平均值检测和输出幅度设定电路（11） 来自可变增益放大器（3）的输出信号的电压，并将可变增益放大器（3）的期望输出幅度的电压½加到平均电压上;以及高增益放大器（12），放大输出 峰值检测器电路（10）的电压和平均值检测和输出幅度设置电路（11）的输出电压，并且使用放大结果作为增益控制信号来控制可变增益放大器（3）的增益。 峰值检测器电路（10）包括晶体管（Q1，Q2，Q3），电流源（I1）和滤波器电路。 滤波电路包括电阻（Ra）和电容器（C1）的串联连接。

公开(公告)号：US08593201B2

公开(公告)日：2013-11-26

申请号：US13527510

申请日：2012-06-19

申请人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka ,  Makoto Nakamura ,  Koichi Murata ,  Masatoshi Tobayashi ,  Eisuke Tsuchiya

发明人： Kimikazu Sano ,  Hiroyuki Fukuyama ,  Hideyuki Nosaka ,  Makoto Nakamura ,  Koichi Murata ,  Masatoshi Tobayashi ,  Eisuke Tsuchiya

IPC分类号： H03L5/00

CPC分类号： H03K19/017545

摘要： In a signal output circuit, an input buffer externally receives a single-phase switching instruction signal to switch a state of the output circuit a shutdown disable state or a shutdown enable state, and converts and outputs the single-phase switching instruction signal into a differential switching instruction signal. A generation control circuit outputs a generation control signal for controlling generation of a control voltage in the control voltage generation circuit based on the differential switching instruction signal. A control voltage generation circuit outputs the control voltage upon changing a value of the control voltage in accordance with a logic of the single-phase switching instruction signal. An output circuit externally receives a differential input signal, outputs a differential output signal upon impedance-converting the differential input signal, and switches between the shutdown disable state and the shutdown enable state of the differential input signal.

摘要翻译： 在信号输出电路中，输入缓冲器从外部接收单相开关指令信号，以将输出电路的状态切换到关闭禁止状态或关断使能状态，并将单相切换指令信号转换并输出到差分 切换指令信号。 一代控制电路根据差动切换指示信号输出用于控制控制电压产生电路中的控制电压产生的发电控制信号。 控制电压产生电路根据单相切换指令信号的逻辑改变控制电压的值来输出控制电压。 输出电路从外部接收差分输入信号，通过对差分输入信号进行阻抗转换来输出差分输出信号，并在差分输入信号的关断禁止状态和关断使能状态之间切换。

公开(公告)号：US20080226298A1

公开(公告)日：2008-09-18

申请号：US10598089

申请日：2004-09-16

申请人： Hiroyuki Fukuyama ,  Toshihiro Itoh ,  Satoshi Tunashima ,  Kimikazu Sano ,  Koichi Murata ,  Yohtaro Umeda ,  Yasuo Tazoh ,  Hirohiko Sugahara ,  Hiromu Toba ,  Masahiro Muraguchi ,  Senichi Suzuki ,  Seiji Fukushima ,  Yoshinori Hibino ,  Tadashi Sakamoto ,  Yoshiaki Yamabayashi ,  Eiji Yoshida ,  Ryuichi Iwamoto

发明人： Hiroyuki Fukuyama ,  Toshihiro Itoh ,  Satoshi Tunashima ,  Kimikazu Sano ,  Koichi Murata ,  Yohtaro Umeda ,  Yasuo Tazoh ,  Hirohiko Sugahara ,  Hiromu Toba ,  Masahiro Muraguchi ,  Senichi Suzuki ,  Seiji Fukushima ,  Yoshinori Hibino ,  Tadashi Sakamoto ,  Yoshiaki Yamabayashi ,  Eiji Yoshida ,  Ryuichi Iwamoto

IPC分类号： H04B10/13

CPC分类号： H04B10/2572

摘要： The present invention has been achieved to provide a novel optical transmission system realizing high-speed optical transmission over greater distance by suppressing waveform degradation caused by mode dispersion and mode transition in a multimode optical transmission line. The optical transmission system of the present invention includes: an optical transmitter for transmitting incoherent light; an excitation mechanism for exciting a predetermined mode in the incoherent light transmitted from the optical transmitter; a multimode optical transmission line for transmitting the incoherent light transmitted from the excitation mechanism; a transmission mechanism for transmitting a predetermined mode in the incoherent light transmitted from the excitation mechanism; and an optical receiver for receiving the incoherent light transmitted from the transmission mechanism or the incoherent light transmitted from the transmission mechanism.

摘要翻译： 本发明是为了提供一种新颖的光传输系统，其通过抑制由多模光传输线路中的模式色散和模式转变引起的波形劣化而实现更大距离的高速光传输。 本发明的光传输系统包括：用于发送非相干光的光发射机; 激励机构，用于激发从所述光发射机发射的非相干光中的预定模式; 用于发送从激励机构发送的非相干光的多模光传输线; 用于在从激励机构发送的非相干光中发送预定模式的传输机构; 以及用于接收从传输机构传输的非相干光或从传输机构发射的非相干光的光接收机。

公开(公告)号：US07249295B2

公开(公告)日：2007-07-24

申请号：US10400452

申请日：2003-03-28

申请人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

发明人： Hiroyuki Fukuyama ,  Takeru Yonaga ,  Hitoshi Tanaka

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/30 ,  G11C2029/0405 ,  G11C2029/3202

摘要： A semiconductor test circuit including an input terminal, a controller, a setting circuit, a command generator, a transmission path switching circuit and a comparator. The input terminal receives serial data including a command code and control data. The controller receives a control signal from the input terminal and outputs an internal control signal. The setting circuit receives serial data from the input terminal and outputs it to the command generator in response to the internal control signal. The command generator then generates an interface signal based on this serial data. The switching circuit receives the signal from one of its ports and outputs the received signal to another port in response to the internal control signal and the command code, and the comparator compares the interface signal received from the command generator with the signal received from the switching circuit.

摘要翻译： 包括输入端子，控制器，设定电路，命令发生器，传输路径切换电路和比较器的半导体测试电路。 输入端子接收包括命令码和控制数据的串行数据。 控制器从输入端接收控制信号并输出​​内部控制信号。 设置电路从输入端接收串行数据，并根据内部控制信号将其输出到命令发生器。 然后，命令生成器基于该串行数据生成接口信号。 开关电路从其一个端口接收信号，并响应于内部控制信号和命令码将接收到的信号输出到另一端口，并且比较器将从命令发生器接收的接口信号与从切换接收的信号进行比较 电路。