公开(公告)号：US07724029B1

公开(公告)日：2010-05-25

申请号：US12502141

申请日：2009-07-13

申请人： Satwant Singh ,  Fabiano Fontana ,  David Chang

发明人： Satwant Singh ,  Fabiano Fontana ,  David Chang

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/17784

摘要： In one embodiment, an integrated circuit (IC) such as a programmable logic device includes a plurality of IC input terminals and an input buffer having a buffer input terminal and a buffer output terminal. A multiplexer is adapted to selectively couple an IC input terminal to the buffer input terminal or to couple the buffer output terminal to the buffer input terminal.

摘要翻译： 在一个实施例中，诸如可编程逻辑器件的集成电路（IC）包括多个IC输入端子和具有缓冲器输入端子和缓冲器输出端子的输入缓冲器。 复用器适于选择性地将IC输入端子耦合到缓冲器输入端子或将缓冲器输出端子耦合到缓冲器输入端子。

公开(公告)号：US20060145238A1

公开(公告)日：2006-07-06

申请号：US11029950

申请日：2005-01-05

申请人： Fabiano Fontana ,  Steven Fong ,  Sunil Mehta ,  Yongzhong Hu

发明人： Fabiano Fontana ,  Steven Fong ,  Sunil Mehta ,  Yongzhong Hu

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/04 ,  H01L27/0255

摘要： One embodiment of the invention is an integrated circuit having: (i) an array of flash transistors formed on a substrate and arranged in one or more rows, each flash transistor having a control gate, wherein, in each row, the control gates are connected to a word line; and (ii) for each word line, at least one diode structure formed on the substrate and having first and second diodes, each diode having a cathode and an anode, wherein the word line is connected to the cathode of the first diode and to the anode of the second diode.

摘要翻译： 本发明的一个实施例是一种集成电路，其具有：（i）形成在衬底上并布置成一行或多行的闪存晶体管阵列，每个闪存晶体管具有控制栅极，其中在每行中连接控制栅极 到字线 和（ii）对于每个字线，形成在所述衬底上并具有第一和第二二极管的至少一个二极管结构，每个二极管具有阴极和阳极，其中所述字线连接到所述第一二极管的阴极和 第二二极管的阳极。

公开(公告)号：US06838904B1

公开(公告)日：2005-01-04

申请号：US10640828

申请日：2003-08-13

申请人： Om P. Agrawal ,  Fabiano Fontana ,  Gilles M. Bosco

发明人： Om P. Agrawal ,  Fabiano Fontana ,  Gilles M. Bosco

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736

摘要： Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., ≦80PTs) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

公开(公告)号：US6133769A

公开(公告)日：2000-10-17

申请号：US201081

申请日：1998-11-30

申请人： Fabiano Fontana ,  Mathew Anton Rybicki ,  Ammisetti V. Prasad

发明人： Fabiano Fontana ,  Mathew Anton Rybicki ,  Ammisetti V. Prasad

IPC分类号： H03L7/089 ,  H03L7/095 ,  H03L7/18 ,  H03L7/06

CPC分类号： H03L7/18 ,  H03L7/0891 ,  H03L7/095

摘要： A phase locked loop comprises a phase locking circuit (16) which includes a phase/frequency detector (18) capable of outputting up and down signals to a charge pump (22) through separate signal paths (24, 26) and a phase lock detector (34) coupled to receive the up and down signals. The phase lock detector (34) determines the difference between the up and down signals from the phase/frequency detector (18) and in response generates a phase lock indicator signal PLL.sub.-- OUT.

摘要翻译： 锁相环包括相位锁定电路（16），该锁相电路包括能够通过分离的信号路径（24,26）向电荷泵（22）输出上下信号的相位/频率检测器（18）和相位锁定检测器 （34），用于接收上下信号。 相位锁定检测器（34）确定来自相位/频率检测器（18）的上升和下降信号之间的差异，并且响应产生锁相指示器信号PLL-OUT。

公开(公告)号：US5568066A

公开(公告)日：1996-10-22

申请号：US341432

申请日：1994-11-17

申请人： Bradley A. Sharpe-Geisler ,  Fabiano Fontana

发明人： Bradley A. Sharpe-Geisler ,  Fabiano Fontana

IPC分类号： H03K19/0185 ,  H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17708 ,  H03K19/018521

摘要： A high density programmable logic device (PLD) having sense amplifiers and OR gates configured to increase operation speed and reduce transistor count from previous circuits as well as to provide a selectable power down mode on a macrocell-by-macrocell basis. The sense amplifiers include a single cascode in the data path connecting a product term to the OR gates. The OR gates utilize a plurality of source follower transistors followed by pass gates to provide logic allocation enabling the sense amplifier outputs to be reduced from the 0.0 V-5.0 V CMOS rails to increase switching speed while reducing overall transistor count. Amplifying inverters normally provided in the sense amplifiers to provide the CMOS rail-to-rail switching and which would require complex feedback for providing power down on a macrocell-by-macrocell basis are moved forward into OR output circuits. Power down on a macrocell-by-macrocell basis is provided by selectively sizing the amplifying inverters in the OR output circuits.

摘要翻译： 具有读出放大器和OR门的高密度可编程逻辑器件（PLD）被配置为增加操作速度并减少来自先前电路的晶体管数量，以及在逐个宏单元的基础上提供可选择的掉电模式。 读出放大器包括将产品项连接到OR门的数据路径中的单个共源共栅。 OR门使用多个源极跟随器晶体管，随后是通过栅极，以提供逻辑分配，使得能够从0.0V-5.0V CMOS轨道减小读出放大器的输出，从而提高开关速度，同时降低总体晶体管数量。 通常在读出放大器中提供的放大反相器，以提供CMOS轨到轨开关，并且这将需要复杂的反馈以便在宏单元逐宏基础上提供掉电向前进入OR输出电路。 通过在OR输出电路中选择性地调整放大逆变器来提供基于宏小区的宏单元的功率下降。

公开(公告)号：US5442304A

公开(公告)日：1995-08-15

申请号：US137437

申请日：1993-10-15

申请人： Jack T. Wong ,  Fabiano Fontana ,  Martha Chan

发明人： Jack T. Wong ,  Fabiano Fontana ,  Martha Chan

IPC分类号： H03K19/00 ,  H03K19/017 ,  H03K19/01 ,  H03K19/0175

CPC分类号： H03K19/0013 ,  H03K19/01721

摘要： A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.

摘要翻译： 公开了一种门钳位电路，其包括逻辑门和偏置电路装置。 通过该钳位电路，在输出信号的低电平至高电平和高电平至低电平转换期间电路的运行速度得到优化，同时功耗最小化。

公开(公告)号：US5418482A

公开(公告)日：1995-05-23

申请号：US138532

申请日：1993-10-15

申请人： Jack T. Wong ,  Fabiano Fontana ,  Martha Chan

发明人： Jack T. Wong ,  Fabiano Fontana ,  Martha Chan

IPC分类号： H03K17/00 ,  H03K17/042 ,  H03F3/18 ,  H03K17/04

CPC分类号： H03K17/04206 ,  H03K2217/0036

摘要： A sense amplifier is provided that has improved speed from input to output, particularly during low-to-high transitions on the output and minimizes power consumption. By removing the product term window circuit from the critical node, the overall speed of the amplifier is maximized. In addition, circuitry is included to speed up low-to-high transitions, high-to-low transitions and provide increased noise immunity over temperature variations.

摘要翻译： 提供了一种读出放大器，其具有从输入到输出的改进速度，特别是在输出端的低到高转换期间，并最大限度地降低功耗。 通过从关键节点移除产品术语窗口电路，放大器的总体速度最大化。 此外，还包括电路，以加速从低到高的转换，从高到低的转换，并提供相对于温度变化提高的抗噪声能力。

公开(公告)号：US07560953B1

公开(公告)日：2009-07-14

申请号：US12107883

申请日：2008-04-23

申请人： Satwant Singh ,  Fabiano Fontana ,  David Chang

发明人： Satwant Singh ,  Fabiano Fontana ,  David Chang

IPC分类号： H03K19/173

CPC分类号： H03K19/17744 ,  H03K19/17784

摘要： A programmable logic device, in accordance with an embodiment, includes a first terminal; an input buffer having a buffer input terminal and a buffer output terminal; and a multiplexer coupled to the first terminal and to the input buffer, wherein the multiplexer is adapted to selectively couple either the first terminal to the buffer input terminal or couple the buffer output terminal to the buffer input terminal.

摘要翻译： 根据实施例的可编程逻辑器件包括第一端子; 具有缓冲器输入端子和缓冲器输出端子的输入缓冲器; 以及耦合到所述第一终端和所述输入缓冲器的多路复用器，其中所述多路复用器适于选择性地将所述第一终端耦合到所述缓冲器输入端子或将所述缓冲器输出端子耦合到所述缓冲器输入端子。

公开(公告)号：US07554358B1

公开(公告)日：2009-06-30

申请号：US11397985

申请日：2006-04-05

申请人： Fabiano Fontana ,  Henry Law ,  Howard Tang ,  Om P. Agrawal ,  David L. Rutledge

发明人： Fabiano Fontana ,  Henry Law ,  Howard Tang ,  Om P. Agrawal ,  David L. Rutledge

IPC分类号： H01L25/00

CPC分类号： H03K19/17772 ,  H03K19/1776

摘要： Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks, and a volatile memory to store data within the programmable logic device, with configuration memory adapted to store first configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory of the programmable logic device. The programmable logic device further includes a non-volatile memory adapted to store data provided from the volatile memory.

摘要翻译： 本文公开了系统和方法，以提供用于可编程逻辑器件的改进的非易失性存储技术。 例如，根据本发明的实施例，可编程逻辑器件包括多个逻辑块，多个输入/输出块和用于在可编程逻辑器件内存储数据的易失性存储器，配置存储器适于 存储用于配置逻辑块，输入/输出块和可编程逻辑器件的易失性存储器的第一配置数据。 可编程逻辑器件还包括适于存储从易失性存储器提供的数据的非易失性存储器。

公开(公告)号：US07459931B1

公开(公告)日：2008-12-02

申请号：US11398437

申请日：2006-04-05

申请人： Howard Tang ,  Henry Law ,  David L. Rutledge ,  Om P. Agrawal ,  Fabiano Fontana

发明人： Howard Tang ,  Henry Law ,  David L. Rutledge ,  Om P. Agrawal ,  Fabiano Fontana

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K19/17744 ,  H03K19/1776

摘要： Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks, a volatile memory block, and configuration memory cells to store configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory block of the programmable logic device. The programmable logic device further includes circuit techniques for preventing loss of data stored in the volatile memory block due to a reconfiguration. Furthermore, for example, the programmable logic device may further prevent the loss of data stored in user registers or loss of input/output personality due to the reconfiguration.

摘要翻译： 本文公开了系统和方法以提供PLD的重新配置技术。 例如，根据本发明的实施例，可编程逻辑器件包括逻辑块，输入/输出块，易失性存储器块和配置存储器单元，以存储配置逻辑块的配置数据，输入/输出 块和可编程逻辑器件的易失性存储器块。 可编程逻辑器件还包括用于防止由于重新配置而存储在易失性存储器块中的数据丢失的电路技术。 此外，例如，可编程逻辑器件还可以防止由于重新配置而存储在用户寄存器中的数据的丢失或输入/输出个性的丢失。