公开(公告)号：US06838904B1

公开(公告)日：2005-01-04

申请号：US10640828

申请日：2003-08-13

申请人： Om P. Agrawal ,  Fabiano Fontana ,  Gilles M. Bosco

发明人： Om P. Agrawal ,  Fabiano Fontana ,  Gilles M. Bosco

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736

摘要： Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., ≦80PTs) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

公开(公告)号：US06650142B1

公开(公告)日：2003-11-18

申请号：US10219046

申请日：2002-08-13

申请人： Om P. Agrawal ,  Fabiano Fontana ,  Gilles M. Bosco

发明人： Om P. Agrawal ,  Fabiano Fontana ,  Gilles M. Bosco

IPC分类号： H03K19177

CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17736

摘要： Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., ≧80 PT's) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps-of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

摘要翻译： 提供了结构和技术，用于允许在复杂可编程逻辑器件（CPLD）中发生以下动作中的一个或多个：（1）选择使用快速的分配器旁路路径（例如，快速5-PT路径） 结合块内简单或超分配; （2）为不需要引脚一致性的信号选择使用OSM旁路; （3）自动重新路由输出使能信号，对应于输出信号，这些信号被重新路由以达到引脚一致性的目的; （4）全球可用的输出使能信号的全球分布; （5）选择性使用两级转向来开发复杂的总和集合术语，其中快速路径或简单分配是不够的; 和（6）在每个逻辑块具有约24个或更少的宏单元单元的设计中使用具有阶段2环绕的单向超分配。 提供了用于集中复杂功能信号（例如，> = 80PT）的奇异逻辑块的开发的技术，使得这种复杂功能信号的发展不消耗块间互连资源。 一种CPLD配置方法包括机器实现的步骤 - 首先识别通过在一个逻辑块中的组合简单或超分配开发可实现的中间复杂度功能，以及在相同或第二逻辑块中的快速路径完成; 以及配置CPLD以通过在一个逻辑块中的简单或超分配开发实现在第一识别步骤中识别的一个或多个功能，并且在相同或第二逻辑块中实现快速路径完成。

公开(公告)号：US07957208B1

公开(公告)日：2011-06-07

申请号：US12389149

申请日：2009-02-19

申请人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

发明人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

IPC分类号： G11C7/00

CPC分类号： H03K19/17772 ,  G11C29/028 ,  H03K19/1776

摘要： In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

摘要翻译： 在一个实施例中，可编程逻辑器件包括多个逻辑块; 多个输入/输出块; 易失性配置存储器，其适于存储用于配置逻辑块和输入/输出块的配置数据; 适用于存储用户数据的嵌入式块RAM; 闪存具有至少第一分区和第二分区; 以及适于提供对所述非易失性存储器的所述第一分区的外部设备访问的数据端口。 闪存适于在数据端口内的第一分区用户数据内存储，并且还适于在第二分区用户内存储来自嵌入式块RAM的数据。

公开(公告)号：US07554358B1

公开(公告)日：2009-06-30

申请号：US11397985

申请日：2006-04-05

申请人： Fabiano Fontana ,  Henry Law ,  Howard Tang ,  Om P. Agrawal ,  David L. Rutledge

发明人： Fabiano Fontana ,  Henry Law ,  Howard Tang ,  Om P. Agrawal ,  David L. Rutledge

IPC分类号： H01L25/00

CPC分类号： H03K19/17772 ,  H03K19/1776

摘要： Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks, and a volatile memory to store data within the programmable logic device, with configuration memory adapted to store first configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory of the programmable logic device. The programmable logic device further includes a non-volatile memory adapted to store data provided from the volatile memory.

摘要翻译： 本文公开了系统和方法，以提供用于可编程逻辑器件的改进的非易失性存储技术。 例如，根据本发明的实施例，可编程逻辑器件包括多个逻辑块，多个输入/输出块和用于在可编程逻辑器件内存储数据的易失性存储器，配置存储器适于 存储用于配置逻辑块，输入/输出块和可编程逻辑器件的易失性存储器的第一配置数据。 可编程逻辑器件还包括适于存储从易失性存储器提供的数据的非易失性存储器。

公开(公告)号：US07459931B1

公开(公告)日：2008-12-02

申请号：US11398437

申请日：2006-04-05

申请人： Howard Tang ,  Henry Law ,  David L. Rutledge ,  Om P. Agrawal ,  Fabiano Fontana

发明人： Howard Tang ,  Henry Law ,  David L. Rutledge ,  Om P. Agrawal ,  Fabiano Fontana

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K19/17744 ,  H03K19/1776

摘要： Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks, a volatile memory block, and configuration memory cells to store configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory block of the programmable logic device. The programmable logic device further includes circuit techniques for preventing loss of data stored in the volatile memory block due to a reconfiguration. Furthermore, for example, the programmable logic device may further prevent the loss of data stored in user registers or loss of input/output personality due to the reconfiguration.

摘要翻译： 本文公开了系统和方法以提供PLD的重新配置技术。 例如，根据本发明的实施例，可编程逻辑器件包括逻辑块，输入/输出块，易失性存储器块和配置存储器单元，以存储配置逻辑块的配置数据，输入/输出 块和可编程逻辑器件的易失性存储器块。 可编程逻辑器件还包括用于防止由于重新配置而存储在易失性存储器块中的数据丢失的电路技术。 此外，例如，可编程逻辑器件还可以防止由于重新配置而存储在用户寄存器中的数据的丢失或输入/输出个性的丢失。

公开(公告)号：US07378873B1

公开(公告)日：2008-05-27

申请号：US11446548

申请日：2006-06-02

申请人： Howard Tang ,  Om P. Agrawal ,  David L. Rutledge ,  Fabiano Fontana

发明人： Howard Tang ,  Om P. Agrawal ,  David L. Rutledge ,  Fabiano Fontana

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17744

摘要： Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). For example, in accordance with one embodiment of the present invention, a PLD includes volatile memory adapted to store configuration data to configure the PLD for its intended function. The PLD further includes non-volatile memory adapted to store configuration data which is transferable to the volatile memory to configure the PLD for its intended function. The PLD further includes a serial peripheral interface (SPI) port adapted to receive configuration data from an external device for transfer into one of the volatile memory and the non-volatile memory.

摘要翻译： 本文公开了系统和方法，以提供诸如可编程逻辑器件（PLD）之类的集成电路的配置的改进方法。 例如，根据本发明的一个实施例，PLD包括适于存储配置数据以便为其功能配置PLD的易失性存储器。 PLD还包括适于存储配置数据的非易失性存储器，其可转移到易失性存储器以根据其预期功能配置PLD。 PLD还包括串行外设接口（SPI）端口，适于从外部设备接收配置数据，以传输到易失性存储器和非易失性存储器之一。

公开(公告)号：US07702977B1

公开(公告)日：2010-04-20

申请号：US12480565

申请日：2009-06-08

申请人： Howard Tang ,  Om P. Agrawal ,  Fabiano Fontana

发明人： Howard Tang ,  Om P. Agrawal ,  Fabiano Fontana

IPC分类号： G01R31/28 ,  G06F21/00

CPC分类号： G06F21/76

摘要： In one embodiment, a programmable logic device includes a first multiplexer; a first memory adapted to store an identification code of the programmable logic device; and a second memory adapted to store an identification code of the programmable logic device. Inputs of a second multiplexer are coupled to the first memory and the second memory, and an output of the multiplexer is coupled to an input of the first multiplexer. The second multiplexer is adapted to select between the identification code stored in the first memory and the identification code stored in the second memory to provide the selected identification code to the first multiplexer.

摘要翻译： 在一个实施例中，可编程逻辑器件包括第一多路复用器; 适于存储可编程逻辑器件的识别码的第一存储器; 以及适于存储可编程逻辑器件的识别码的第二存储器。 第二多路复用器的输入耦合到第一存储器和第二存储器，并且多路复用器的输出耦合到第一多路复用器的输入端。 第二多路复用器适于在存储在第一存储器中的识别码与存储在第二存储器中的识别码之间进行选择，以将所选择的识别码提供给第一多路复用器。

公开(公告)号：US07546498B1

公开(公告)日：2009-06-09

申请号：US11446308

申请日：2006-06-02

申请人： Howard Tang ,  Om P. Agrawal ,  Fabiano Fontana

发明人： Howard Tang ,  Om P. Agrawal ,  Fabiano Fontana

IPC分类号： G01R31/28 ,  G06F21/00

CPC分类号： G06F21/76

摘要： Systems and methods are disclosed herein to provide techniques for providing programmable identification codes (IDCODE) for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first non-volatile memory adapted to store a first identification code of the programmable logic device, and a second memory adapted to store a second identification code of the programmable logic device. A control circuit selects between the first identification code stored in the first non-volatile memory and the second identification code stored in the second memory to provide as an identification code for the programmable logic device.

摘要翻译： 本文公开了提供用于为PLD提供可编程识别码（IDCODE）的技术的系统和方法。 例如，根据本发明的实施例，可编程逻辑器件包括适于存储可编程逻辑器件的第一识别码的第一非易失性存储器，以及适于存储可编程逻辑器件的第二识别码的第二存储器 可编程逻辑器件。 控制电路在存储在第一非易失性存储器中的第一识别码与存储在第二存储器中的第二识别码之间进行选择，以提供可编程逻辑器件的识别码。

公开(公告)号：US07495970B1

公开(公告)日：2009-02-24

申请号：US11446309

申请日：2006-06-02

申请人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

发明人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

IPC分类号： G11C7/10

CPC分类号： H03K19/17772 ,  G11C29/028 ,  H03K19/1776

摘要： Systems and methods provide non-volatile memory architectures for programmable logic devices. For example, a programmable logic device may include logic blocks, input/output blocks, and configuration memory to store configuration data for configuration of the logic blocks and the input/output blocks. A first non-volatile memory may store user information, besides configuration data, and a first port includes a dedicated serial peripheral interface to provide access to the first non-volatile memory.

摘要翻译： 系统和方法为可编程逻辑器件提供非易失性存储器架构。 例如，可编程逻辑器件可以包括逻辑块，输入/输出块和配置存储器，以存储用于配置逻辑块和输入/输出块的配置数据。 除了配置数据之外，第一非易失性存储器可以存储用户信息，并且第一端口包括用于提供对第一非易失性存储器的访问的专用串行外围接口。

公开(公告)号：US08553463B1

公开(公告)日：2013-10-08

申请号：US13052142

申请日：2011-03-21

申请人： Robert Gary Pollachek ,  Loren Mclaury ,  Fabiano Fontana

发明人： Robert Gary Pollachek ,  Loren Mclaury ,  Fabiano Fontana

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C16/16

摘要： In one embodiment, a voltage discharge (VD) system has a slow VD subsystem that provides two concurrent discharge current paths to at least begin to discharge both positive and negative voltages: a first path from the positive-voltage node to ground and a second path from the positive-voltage node to the negative-voltage node. In addition to this relatively slow VD subsystem, the VD system can also have a conventional fast VD subsystem that is turned on after the slow VD subsystem has reduced the positive and negative voltages to some degree (e.g., half of each charge removed). Such a VD system can eliminate dangerous overshoot conditions, even when control-signal skew is present.

摘要翻译： 在一个实施例中，电压放电（VD）系统具有缓慢的VD子系统，其提供两个并发的放电电流路径，以至少开始放电正电压和负电压：从正电压节点到地的第一路径和第二路径 从正电压节点到负电压节点。 除了这种相对较慢的VD子系统之外，VD系统还可以具有传统的快速VD子系统，其在慢VD子系统在一定程度上减小正电压和负电压（例如，每个电荷被移除的一半）之后被接通。 即使存在控制信号偏移，这种VD系统也可以消除危险的过冲条件。