公开(公告)号：US06509615B2

公开(公告)日：2003-01-21

申请号：US10067791

申请日：2002-02-08

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H01L31119

CPC分类号： H01L21/76229 ,  H01L21/823807 ,  H01L29/783

摘要： A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.

摘要翻译： 具有动态阈值晶体管的半导体器件包括由浅沟槽隔离构成的浅元件隔离区域和设置在浅元件隔离区域两侧的深元件隔离区域构成的复合元件隔离区域。 由于浅元件隔离区域由浅沟槽隔离构成，浅元件隔离区域中的鸟喙小。 这可以防止由于鸟嘴引起的应力引起的泄漏故障。 深元件隔离区域具有近似恒定的宽度，其允许复杂元件隔离区域宽。

公开(公告)号：US20020105034A1

公开(公告)日：2002-08-08

申请号：US10067791

申请日：2002-02-08

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto

IPC分类号： H01L029/76

CPC分类号： H01L21/76229 ,  H01L21/823807 ,  H01L29/783

摘要： A semiconductor device with dynamic threshold transistors includes a complex element isolation region composed of a shallow element isolation region made of shallow trench isolation and deep element isolation regions provided on both sides of the shallow element isolation region. Since the shallow element isolation region is made of the shallow trench isolation, Bird's beak in the shallow element isolation region is small. This prevents off leakage failure due to stress caused by the bird's beak. The deep element isolation region has an approximately constant width which allows the complex element isolation region to be wide.

摘要翻译： 具有动态阈值晶体管的半导体器件包括由浅沟槽隔离构成的浅元件隔离区域和设置在浅元件隔离区域两侧的深元件隔离区域构成的复合元件隔离区域。 由于浅元件隔离区域由浅沟槽隔离构成，浅元件隔离区域中的鸟喙小。 这可以防止由于鸟嘴引起的应力引起的泄漏故障。 深元件隔离区域具有近似恒定的宽度，其允许复杂元件隔离区域宽。

公开(公告)号：US06303444B1

公开(公告)日：2001-10-16

申请号：US09693715

申请日：2000-10-19

申请人： James B. Burr

发明人： James B. Burr

IPC分类号： H01L21336

CPC分类号： H01L21/823892 ,  H01L27/0738 ,  H01L27/0921 ,  H01L29/1083 ,  H01L29/78 ,  H01L29/783

摘要： A method for providing low power MOS devices that include buried wells specifically designed to provide a resistive path between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between clock cycles.

摘要翻译： 一种用于提供低功率MOS器件的方法，其包括专门设计用于在器件的散装材料和阱接触之间提供电阻路径的掩埋阱。 通过提供电阻路径，将等效的RC电路引入器件，其允许体材料电势跟踪栅极电位，从而有利地降低器件导通时的阈值电压，并在器件关断时提高阈值电压。 此外，引入电阻路径还允许大量材料电位被控制并且稳定在时钟周期之间的平衡电位。

公开(公告)号：US5780899A

公开(公告)日：1998-07-14

申请号：US534527

申请日：1995-09-27

申请人： Chenming Hu ,  Hsing-Jen Wann

发明人： Chenming Hu ,  Hsing-Jen Wann

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01 ,  H01L29/94

CPC分类号： H01L27/092 ,  H01L29/783 ,  H01L29/7838 ,  H01L29/78606 ,  H01L29/78696

摘要： A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. The channel region is delta-doped or counter-doped which permits superior performance for high-end VSLI applications. A selective epitaxy on a counter-doped substrate can be used in a counter-doped device. Doped wells can be used in a bulk silicon substrate in forming the devices. Trenching can be used to isolate devices in the doped wells.

摘要翻译： 诸如MOSFET的动态阈值电压IGFET可在0.6伏或更小的电压下工作。 通过互连栅极接触和电压控制通道所在的器件主体，将晶体管的阈值电压降低到零伏特以下。 沟道区域是δ掺杂或反掺杂的，这为高端VSLI应用提供了优异的性能。 反掺杂衬底上的选择性外延可以用在反掺杂器件中。 掺杂的阱可以用于体硅衬底中以形成器件。 沟渠可用于隔离掺杂井中的设备。

公开(公告)号：US20240316674A1

公开(公告)日：2024-09-26

申请号：US18733522

申请日：2024-06-04

申请人： Illinois Tool Works Inc.

发明人： Andrew Joseph Henry

IPC分类号： B23K9/10 ,  H01F27/28 ,  H01L29/739 ,  H01L29/78

CPC分类号： B23K9/1043 ,  B23K9/1056 ,  H01F27/28 ,  H01L29/7393 ,  H01L29/783

摘要： An example welding-type power supply includes: a transformer having a primary winding and first and second secondary windings; an input circuit configured to provide an input voltage to the primary winding of the transformer; first, second, third, and fourth switching elements, and a control circuit configured to: control the first, second, third, and fourth switching elements to selectively output a positive or negative output voltage without a separate rectifier stage by selectively controlling ones of the first, second, third, and fourth switching elements based on a commanded output voltage polarity and an input voltage polarity to the transformer; and prior to changing from a first output voltage polarity to a second output voltage polarity, controlling the first, second, third, and fourth switching elements to reverse the power flow to return reactive energy to an input circuit via the transformer.

公开(公告)号：US20230207704A1

公开(公告)日：2023-06-29

申请号：US17561589

申请日：2021-12-23

申请人： Dan S. LAVRIC ,  YenTing CHIU ,  Mohit K. HARAN ,  Allen B. GARDINER ,  Leonard P. GULER ,  Andy Chih-Hung WEI ,  Tahir GHANI

发明人： Dan S. LAVRIC ,  YenTing CHIU ,  Mohit K. HARAN ,  Allen B. GARDINER ,  Leonard P. GULER ,  Andy Chih-Hung WEI ,  Tahir GHANI

IPC分类号： H01L29/808 ,  H01L29/80 ,  H01L29/78

CPC分类号： H01L29/808 ,  H01L29/802 ,  H01L29/783

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures. Other embodiments may be described or claimed.

公开(公告)号：US20180261607A1

公开(公告)日：2018-09-13

申请号：US15975761

申请日：2018-05-09

申请人： Renesas Electronics Corporation

发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

IPC分类号： H01L27/11 ,  H01L29/49 ,  H01L29/78 ,  G11C11/412 ,  G11C11/417

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

公开(公告)号：US09985038B2

公开(公告)日：2018-05-29

申请号：US15448585

申请日：2017-03-02

申请人： Renesas Electronics Corporation

发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

IPC分类号： H01L27/11 ,  G11C11/412 ,  G11C11/417 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

公开(公告)号：US09773782B2

公开(公告)日：2017-09-26

申请号：US15369951

申请日：2016-12-06

申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

发明人： Trudy Benjamin

IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  B41J2/14 ,  H01L29/10

CPC分类号： H01L27/0629 ,  B41J2/1433 ,  B41J2002/14491 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/1033 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/783

摘要： In some examples, a transistor includes a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

公开(公告)号：US09646678B2

公开(公告)日：2017-05-09

申请号：US15216327

申请日：2016-07-21

申请人： Renesas Electronics Corporation

发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/417

CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.