公开(公告)号：US10812089B2

公开(公告)日：2020-10-20

申请号：US16357169

申请日：2019-03-18

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Edward Lee ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans

IPC: H03L7/099 ,  H03K19/177 ,  H03L7/08

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

公开(公告)号：US10598852B1

公开(公告)日：2020-03-24

申请号：US16425009

申请日：2019-05-29

Applicant: Xilinx, Inc.

Inventor： Hai bing Zhao ,  Kee Hian Tan ,  Ping-Chuan Chiang ,  Yipeng Wang ,  Yohan Frans

IPC: G09G3/36 ,  G02B6/12 ,  H03M1/50 ,  G02B6/42

Abstract: A data driver includes pre-driver circuitry coupled to a digital-to-analog converter (DAC) via a plurality of bit lines. The pre-driver circuitry is configured to receive a plurality of first voltages corresponding to respective bits of a digital codeword. Each of the first voltages may have one of a first voltage value or a ground potential based on a value of the corresponding bit. The pre-driver circuitry is further configured to drive a plurality of second voltages onto the plurality of bit lines, respectively, by switchably coupling each of the bit lines to ground or a voltage rail based at least in part on the voltage values of the plurality of first voltages. The voltage rail provides a second voltage value that is greater than the first voltage value. The DAC converts the plurality of second voltages to an electrical signal which is an analog representation of the digital codeword.

公开(公告)号：US10256968B1

公开(公告)日：2019-04-09

申请号：US15660141

申请日：2017-07-26

Applicant: Xilinx, Inc.

Inventor： Zhaoyin D. Wu ,  Yu Xu ,  Winson Lin ,  Yohan Frans ,  Geoffrey Zhang

IPC: H04L7/00 ,  H03L7/081 ,  H04L7/033

Abstract: A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

公开(公告)号：US09960844B1

公开(公告)日：2018-05-01

申请号：US15474588

申请日：2017-03-30

Applicant: Xilinx, Inc.

Inventor： Mayank Raj ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04B10/00 ,  H04B10/077 ,  H04B10/60

CPC classification number: H04B10/0775 ,  G01R31/2635 ,  H03K17/78 ,  H04B10/60

Abstract: An example photodiode emulator circuit includes: a first current source circuit; first and second transistors having sources coupled together and coupled to an output of the first current source circuit, a drain of the second transistor coupled to a first node; a third transistor coupled between a drain of the first transistor and a replica load circuit; a second current source circuit coupled to the first node; a capacitor coupled between the first node and electrical ground; and a fourth transistor having a source coupled to the first node and a drain that supplies an output current.

公开(公告)号：US09602082B2

公开(公告)日：2017-03-21

申请号：US14814401

申请日：2015-07-30

Applicant: Xilinx, Inc.

Inventor： Hiva Hedayati ,  Yohan Frans

IPC: H03K3/017

CPC classification number: H03K3/017 ,  G06F1/04 ,  H03K5/1565

Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit. A digital value is used by a feedback algorithm to correct the clock distortion.

公开(公告)号：US09356775B1

公开(公告)日：2016-05-31

申请号：US14795169

申请日：2015-07-09

Applicant: Xilinx, Inc.

Inventor： Yu Xu ,  Cheng-Hsiang Hsieh ,  Yohan Frans ,  Kun-Yung Chang

IPC: H04L7/033 ,  H04L7/04

CPC classification number: H04L7/041 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337

Abstract: Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code or a crossing PI code in a clock and data recovery (CDR) circuit until one or more preset criteria are satisfied. One example method generally includes determining that a condition has been met; based on the determination, stepping, in a CDR circuit, at least one of a data PI code or a crossing PI code for each cycle of a clock; stopping the stepping based on one or more criteria to generate a predetermined state of the data PI code and the crossing PI code, wherein the predetermined state comprises an offset between the data PI code and the crossing PI code; receiving a data stream; and performing clock and data recovery on the data stream based on the offset between the data PI code and the crossing PI code.

Abstract translation: 描述了用于在时钟和数据恢复（CDR）电路中同步地步进数据相位内插器（PI）代码或交叉PI代码中的至少一个的方法和装置，直到满足一个或多个预设标准。 一个示例性方法通常包括确定已经满足条件; 基于所述确定，在CDR电路中步进每个时钟周期的数据PI代码或交叉PI代码中的至少一个; 基于一个或多个标准停止步进以产生数据PI代码和交叉PI代码的预定状态，其中预定状态包括数据PI代码和交叉PI代码之间的偏移量; 接收数据流; 并且基于数据PI代码和交叉PI代码之间的偏移在数据流上执行时钟和数据恢复。

公开(公告)号：US12072239B1

公开(公告)日：2024-08-27

申请号：US18128948

申请日：2023-03-30

Applicant: XILINX, INC.

Inventor： Zhaowen Wang ,  Mayank Raj ,  Chuan Xie ,  Sandeep Kumar ,  Muqseed Mohammad ,  Sukruth Pattanagiri Giriyappa ,  Stanley Y. Chen ,  Parag Upadhyaya ,  Yohan Frans

IPC: G01J1/44 ,  G01J1/02 ,  H03F3/45

CPC classification number: G01J1/44 ,  G01J1/0252 ,  H03F3/45076 ,  G01J2001/444 ,  G01J2001/446

Abstract: An integrated circuit (IC) device includes a controller circuitry having an input coupled to a photodiode of an optoelectronic circuitry and an output coupled to a heater of the optoelectronic circuitry, the controller circuitry configured to determine a center frequency of the optoelectronic circuitry based on a shape of an input signal received from the photodiode, and provide a heater signal to the heater based on the shape of the input signal and the center frequency of the optoelectronic circuitry.

公开(公告)号：US11043470B2

公开(公告)日：2021-06-22

申请号：US16694476

申请日：2019-11-25

Applicant: XILINX, INC.

Inventor： Jing Jing ,  Shuxian Wu ,  Xin X. Wu ,  Yohan Frans

IPC: H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L25/00 ,  H01L49/02 ,  H01L21/48 ,  H01L23/538

Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

公开(公告)号：US20200304130A1

公开(公告)日：2020-09-24

申请号：US16357169

申请日：2019-03-18

Applicant: Xilinx, Inc.

Inventor： Caleb S. Leung ,  Edward Lee ,  Alan C. Wong ,  Christopher J. Borrelli ,  Yohan Frans

IPC: H03L7/099 ,  H03L7/08 ,  H03K19/177

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

公开(公告)号：US10530375B1

公开(公告)日：2020-01-07

申请号：US16122761

申请日：2018-09-05

Applicant: Xilinx, Inc.

Inventor： Yipeng Wang ,  Kee Hian Tan ,  Stanley Y. Chen ,  Yohan Frans

IPC: H03B19/12 ,  H03L7/197 ,  H03L7/193

Abstract: A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.