公开(公告)号：US20180166333A1

公开(公告)日：2018-06-14

申请号：US15675498

申请日：2017-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76879 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1036

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.

公开(公告)号：US20170092591A1

公开(公告)日：2017-03-30

申请号：US15361699

申请日：2016-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Kang FU ,  Hsien-Chang WU ,  Li-Lin SU ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

公开(公告)号：US20230223334A1

公开(公告)日：2023-07-13

申请号：US18173283

申请日：2023-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/7684 ,  H01L21/76832 ,  H01L21/76802 ,  H01L21/76849 ,  H01L23/5283 ,  H01L23/53276 ,  H01L21/768 ,  H01L21/76852 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53252

Abstract: A interconnect structure includes a lower metal, a dielectric layer, an upper metal, and a graphene layer. The dielectric layer laterally surrounds the lower metal. The upper metal is over the lower metal. The graphene layer is over a top surface of the upper metal and opposite side surfaces of the upper metal from a cross-sectional view.

公开(公告)号：US20220384336A1

公开(公告)日：2022-12-01

申请号：US17884301

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Yi YANG ,  Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

公开(公告)号：US20210249299A1

公开(公告)日：2021-08-12

申请号：US16788057

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chin LEE ,  Shao-Kuan LEE ,  Hsin-Yen HUANG ,  Hai-Ching CHEN ,  Shau-Lin SHUE

IPC: H01L21/768

Abstract: A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

公开(公告)号：US20200299129A1

公开(公告)日：2020-09-24

申请号：US16895446

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Ping CHEN ,  Carlos H. DIAZ ,  Ken-Ichi GOTO ,  Shau-Lin SHUE ,  Tai-I YANG

IPC: B82B1/00 ,  B81C1/00 ,  B81B3/00 ,  B82B3/00

Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a first dielectric layer formed over a substrate, and a first conductive layer formed in the first dielectric layer. The NEMS device structure includes a second dielectric layer formed over the first dielectric layer, and a first supporting electrode a second supporting electrode and a beam structure formed in the second dielectric layer. The beam structure is formed between the first supporting electrode and the second supporting electrode, and the beam structure has a T-shaped structure. The NEMS device structure includes a first through hole formed between the first supporting electrode and the beam structure, and a second through hole formed between the second supporting electrode and the beam structure.

公开(公告)号：US20190245054A1

公开(公告)日：2019-08-08

申请号：US16390210

申请日：2019-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-I YANG ,  Yung-Chih WANG ,  Shin-Yi YANG ,  Chih-Wei LU ,  Hsin-Ping CHEN ,  Shau-Lin SHUE

IPC: H01L29/49 ,  H01L29/43 ,  H01L29/12 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L29/49 ,  H01L21/76885 ,  H01L29/0649 ,  H01L29/12 ,  H01L29/435 ,  H01L29/66666 ,  H01L29/78642

Abstract: A vertical MOS transistor includes a substrate, a metal line over the substrate, a semiconductor pillar, a gate dielectric layer surrounding the semiconductor pillar, and a metal gate surrounding the gate dielectric layer. The metal line is under a bottom surface of the semiconductor pillar. The semiconductor pillar is grown by using the bottom-up growing in low temperature to reduce turn off leakage current (Ioff), short channel effect, thermo-budget, and provide high electron mobility.

公开(公告)号：US20190157144A1

公开(公告)日：2019-05-23

申请号：US15820419

申请日：2017-11-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han LEE ,  Shih-Kang FU ,  Meng-Pei LU ,  Shau-Lin SHUE

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/321 ,  H01L23/532

Abstract: A method includes forming a first metal into a first trench in a dielectric layer, performing a thermal treatment to the first metal such that an average grain size of the first metal is increased, and performing a first chemical mechanical polish (CMP) process to the first metal after the performing the thermal treatment.

公开(公告)号：US20180334383A1

公开(公告)日：2018-11-22

申请号：US16009668

申请日：2018-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Ping CHEN ,  Carlos H. DIAZ ,  Ken-Ichi GOTO ,  Shau-Lin SHUE ,  Tai-I YANG

IPC: B82B1/00 ,  B82B3/00

Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a substrate and an interconnect structure formed over the substrate. The NEMS device structure includes a dielectric layer formed over the interconnect structure and a beam structure formed in and over the dielectric layer, wherein the beam structure includes a plurality of strip structures. The NEMS device structure includes a cap structure formed over the dielectric layer and the beam structure and a cavity formed between the beam structure and the cap structure.

公开(公告)号：US20170317010A1

公开(公告)日：2017-11-02

申请号：US15651834

申请日：2017-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Han LEE ,  Shau-Lin SHUE

IPC: H01L23/373 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/3736 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/53276

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer. The method also includes forming a catalyst layer over a sidewall of the opening and forming a conductive element directly on the catalyst layer. The catalyst layer is capable of lowering a formation temperature of the conductive element. The method further includes removing a portion of the conductive element such that the conductive element is within a space surrounded by the catalyst layer.