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公开(公告)号：US20220263409A1
公开(公告)日：2022-08-18
申请号：US17737207
申请日：2022-05-05
Inventor： Chung-Cheng Chou , Tien-Yen Wang
Abstract: A system includes a charge pump system having a plurality of enable signal input terminals and an output terminal, the charge pump system configured to provide an output voltage at the output terminal; and a detection circuit connected to the enable terminals and the output terminal of the charge pump system, the detection circuit configured to compare the charge pump system output voltage to a plurality of predefined input detection voltage levels, and to selectively output a plurality of enable signals to the charge pump system enable signal input terminals in response to the comparison.
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公开(公告)号：US10950303B2
公开(公告)日：2021-03-16
申请号：US16415785
申请日：2019-05-17
Inventor： Chung-Cheng Chou , Pei-Ling Tseng , Zheng-Jun Lin
Abstract: A circuit includes a bias voltage generator and a current limiter. The bias voltage generator is configured to receive a first reference voltage and output a bias voltage responsive to a first current and the first reference voltage. The current limiter is configured to receive a second current at an input terminal, a second reference voltage, and the bias voltage, and, responsive to the second reference voltage and a voltage level of the input terminal, limit the second current to a current limit level, the voltage level of the input terminal being based on the bias voltage.
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公开(公告)号：US09608204B2
公开(公告)日：2017-03-28
申请号：US14021364
申请日：2013-09-09
Inventor： Po-Hao Lee , Chung-Cheng Chou , Wen-Ting Chu
IPC: H01L45/00
CPC classification number: H01L45/1608 , H01L45/08 , H01L45/124 , H01L45/1273 , H01L45/146 , H01L45/1683
Abstract: The present disclosure provides a semiconductor structure which includes a conductive layer and a resistance configurable structure over the conductive layer. The resistance configurable structure includes a first electrode, a resistance configurable layer over the first electrode, and a second electrode over the resistance configurable layer. The first electrode has a first sidewall, a second sidewall, and a bottom surface on the conductive layer. A joint between the first sidewall and the second sidewall includes an electric field enhancement structure. The present disclosure also provides a method for manufacturing the above semiconductor structure, including patterning a hard mask on a conductive layer; forming a spacer around the hard mask; removing at least a portion of the hard mask; forming a conforming resistance configurable layer on the spacer; and forming a second conductive layer on the conforming resistance configurable layer.
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公开(公告)号：US20150187394A1
公开(公告)日：2015-07-02
申请号：US14145700
申请日：2013-12-31
Inventor： Po-Hao Lee , Chung-Cheng Chou
CPC classification number: G11C7/06 , G11C7/065 , G11C11/1673 , G11C13/004 , G11C2013/0054
Abstract: A device includes first and second current mirrors electrically connected to reference and cell current sources of a memory array. A first inverter is electrically connected to the first current mirror, and a second inverter is electrically connected to the second current mirror. The first and second inverters are cross-coupled.
Abstract translation: 一种器件包括电连接到存储器阵列的参考和电池电流源的第一和第二电流镜。 第一逆变器电连接到第一电流镜，第二反相器电连接到第二电流镜。 第一和第二逆变器是交叉耦合的。
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公开(公告)号：US20240355389A1
公开(公告)日：2024-10-24
申请号：US18760971
申请日：2024-07-01
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0033 , G11C2213/79
Abstract: A memory device includes RRAM memory cells configured to form a zero-transistor and one-resistor (0T1R) array structure in which access transistors of the RRAM memory cells are bypassed or removed. Alternatively, the access transistors of the RRAM memory cells may be arranged in a parallel structure to reduce associated IR drop and thus enable reduced write voltage operation.
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Patent Agency Ranking
公开(公告)号：US20240153558A1
公开(公告)日：2024-05-09
申请号：US18411758
申请日：2024-01-12
Inventor： Yu-Der Chih , Chung-Cheng Chou , Chun-Yun Wu , Chen-Ming Hung
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/004 , G11C13/0064
Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
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公开(公告)号：US11942150B2
公开(公告)日：2024-03-26
申请号：US18054359
申请日：2022-11-10
Inventor： Chung-Cheng Chou , Zheng-Jun Lin , Pei-Ling Tseng
CPC classification number: G11C13/0038 , G11C13/003 , G11C2213/15 , G11C2213/79
Abstract: A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.
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公开(公告)号：US11636896B2
公开(公告)日：2023-04-25
申请号：US17103239
申请日：2020-11-24
Inventor： Chin-I Su , Chung-Cheng Chou , Yu-Der Chih , Zheng-Jun Lin
IPC: G11C13/00
Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.
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公开(公告)号：US20220254412A1
公开(公告)日：2022-08-11
申请号：US17470849
申请日：2021-09-09
Inventor： Zheng-Jun Lin , Chin-I Su , Pei-Ling Tseng , Chung-Cheng Chou
IPC: G11C13/00
Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.
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公开(公告)号：US20210118499A1
公开(公告)日：2021-04-22
申请号：US17135169
申请日：2020-12-28
Inventor： Chien-An Lai , Chung-Cheng Chou , Yu-Der Chih
Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
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