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公开(公告)号：US20230075180A1
公开(公告)日：2023-03-09
申请号：US17796916
申请日：2021-01-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Seiichi YONEDA
IPC: H01L21/8238 , H01L27/088 , H01L27/146
Abstract: A semiconductor device that level-shifts a negative voltage and/or a positive voltage is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, an input terminal, and an output terminal. A first terminal of the first transistor is electrically connected to a first terminal of the second transistor and the output terminal. A second terminal of the second transistor is electrically connected to a first terminal of the third transistor. A first terminal of the fourth transistor is electrically connected to a gate of the second transistor and a first terminal of the first capacitor, and a second terminal of the first capacitor is electrically connected to the input terminal. The first transistor, the second transistor, the third transistor, and the fourth transistor are of the same polarity.
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公开(公告)号：US20230054986A1
公开(公告)日：2023-02-23
申请号：US17904400
申请日：2021-02-22
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Seiichi YONEDA , Takayuki IKEDA , Hiroki INOUE , Yusuke NEGORO , Shunpei YAMAZAKI
IPC: H01L27/146
Abstract: An imaging device capable of image processing is provided. The imaging device has an image recognition function. In the imaging device, cells have a function of acquiring imaging data and a function of retaining weight data. Among the cells arranged in a matrix, some of the cells acquire imaging data and the rest of the cells retain weight data. Then, arithmetic operation is performed using the imaging data and the weight data. For example, all the imaging data can be subjected to arithmetic operation where products of the imaging data and the weight data are calculated and the sum of the calculated products is calculated. That is, product-sum operation can be performed. When an arithmetic operation result is captured by a neural network such as a convolutional neural network (CNN) or the like, the additional function can be used because image processing can be performed on the imaging data.
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公开(公告)号：US20220264046A1
公开(公告)日：2022-08-18
申请号：US17628293
申请日：2020-07-13
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Seiichi YONEDA , Yusuke NEGORO , Takahiko ISHIZU , Hidetomo KOBAYASHI
IPC: H04N5/3745 , H04N5/351
Abstract: An imaging device having a motion detecting function and an image processing function is provided. The imaging device can detect a difference between a reference frame image and a comparative frame image, and can switch from a motion detecting mode to a normal image capturing mode when a significant difference is detected. A low-frame-rate operation in the motion detecting mode can reduce power consumption. Moreover, the imaging device has an image recognition function in combination with the motion detecting function, so that switching from the motion detecting mode to the normal image capturing mode can be performed when a particular image is recognized.
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公开(公告)号：US20200343245A1
公开(公告)日：2020-10-29
申请号：US16765398
申请日：2018-11-22
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Shunpei YAMAZAKI , Hajime KIMURA , Munehiro KOZUMA , Takeshi AOKI , Hiroki INOUE , Shintaro HARADA , Daisuke MATSUBAYASHI
IPC: H01L27/105 , H01L27/12 , H01L23/34 , H01L29/786
Abstract: Provided is a storage device that achieves both retention operation at high temperatures and high-speed operation at low temperatures.The storage device includes a driver circuit and a plurality of memory cells, and the memory cell includes a transistor and a capacitor; the transistor includes a metal oxide in a channel formation region. In the case where the transistor includes a first gate and a second gate, the driver circuit has a function of driving the second gate, and the driver circuit outputs a potential corresponding to the temperature of the storage device or the temperature of an environment where the storage device is placed to the second gate in a period during which the memory cell retains data.
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公开(公告)号：US20200295006A1
公开(公告)日：2020-09-17
申请号：US16885742
申请日：2020-05-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Fumika Akasawa , Hiroki INOUE , Takashi NAKAGAWA , Yoshiyuki KUROKAWA
IPC: H01L27/108
Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
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Patent Agency Ranking
公开(公告)号：US20180151593A1
公开(公告)日：2018-05-31
申请号：US15821006
申请日：2017-11-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Fumika AKASAWA
CPC classification number: H01L27/124 , G06F3/0412 , G09G3/3233 , G09G3/3266 , G09G3/3648 , G09G3/3677 , G09G2300/046 , G09G2310/0289 , H01L27/1225 , H01L27/1255 , H03K3/356017
Abstract: A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.
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公开(公告)号：US20170186751A1
公开(公告)日：2017-06-29
申请号：US15390957
申请日：2016-12-27
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Fumika Akasawa , Hiroki INOUE , Takashi NAKAGAWA , Yoshiyuki KUROKAWA
IPC: H01L27/108 , H01L29/16 , H01L23/535 , H01L29/24
CPC classification number: H01L27/10805 , G11C8/08 , G11C11/403 , G11C11/405 , G11C11/4074 , G11C11/4085 , H01L27/10808
Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
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公开(公告)号：US20170154678A1
公开(公告)日：2017-06-01
申请号：US15359017
申请日：2016-11-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takashi NAKAGAWA , Hiroki INOUE , Fumika AKASAWA , Yoshiyuki KUROKAWA
CPC classification number: G11C16/10 , G11C7/1006 , G11C7/16 , G11C8/12 , G11C11/405 , G11C11/4087 , G11C16/0466 , H01L27/1225 , H01L27/124 , H01L27/14616 , H01L27/14636 , H01L27/14643
Abstract: A semiconductor device with an arithmetic processing function is provided. The semiconductor device includes a first circuit and a second circuit each having a function of performing one-dimensional discrete cosine transform. By directly inputting output data of the first circuit to the second circuit, two-dimensional discrete cosine transform can be performed immediately. A memory cell array included in the first circuit is divided into a plurality of memory blocks. In the case where a selection transistor is provided in the memory block, data processing can be performed in each memory block.
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公开(公告)号：US20130335056A1
公开(公告)日：2013-12-19
申请号：US13908121
申请日：2013-06-03
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Hiroki INOUE , Kiyoshi KATO , Shuhei NAGATSUKA , Koichiro KAMATA , Tsutomu MURAKAWA , Takahiro TSUJI , Kaori IKADA
IPC: G05F3/16
Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
Abstract translation: 本发明的一个目的是提供一种具有改善的噪声容限的调节器电路。 在包括基于第一电源端子和第二电源端子之间的电位差产生参考电压的偏置电路的调节器电路中，以及基于参考电位向输出端子输出电位的电压调节器 在偏置电路的输入端，在电源端子与偏置电路中包含的晶体管的栅极连接的节点之间设置有旁路电容器。
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公开(公告)号：US20240305909A1
公开(公告)日：2024-09-12
申请号：US18668606
申请日：2024-05-20
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takeya HIROSE , Seiichi YONEDA , Hiroki INOUE , Takayuki IKEDA , Shunpei YAMAZAKI
IPC: H04N25/705 , H04N25/77 , H04N25/78
CPC classification number: H04N25/705 , H04N25/77 , H04N25/78
Abstract: An imaging device having a function of processing an image is provided. The imaging device has an additional function such as image processing, can hold analog data obtained by an image capturing operation in a pixel, and can extract data obtained by multiplying the analog data by a predetermined weight coefficient. Difference data between adjacent light-receiving devices can be obtained in a pixel, and data on luminance gradient can be obtained. When the data is taken in a neural network or the like, inference of distance data or the like can be performed. Since enormous volume of image data in the state of analog data can be held in pixels, processing can be performed efficiently.
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