公开(公告)号：US20240357800A1

公开(公告)日：2024-10-24

申请号：US18528854

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHO LEE ,  Moonyoung Jeong ,  Sihyun Kim ,  Yoongi Hong

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes a first bit line extending in a first direction, a first semiconductor pattern extending in a second direction and including first and second ends opposite to each other, the first end of the first semiconductor pattern being in contact with the first bit line, a first word line on the first semiconductor pattern and extending in a third direction, a selection line adjacent to the second end of the first semiconductor pattern and parallel to the third direction, a second semiconductor pattern interposed between the selection line and the first semiconductor pattern and having first end and second ends opposite to each other, a second bit line extending in the first direction and in contact with the first end of the second semiconductor pattern, and a source line extending in the first direction and in contact with the second end of the second semiconductor pattern.

公开(公告)号：US20240172428A1

公开(公告)日：2024-05-23

申请号：US18518293

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： KYUNGHWAN KIM ,  Hyungeun Choi ,  Keunnam Kim ,  Seokhan Park ,  Seokho Shin ,  Joongchan Shin ,  Kiseok Lee ,  Sangho Lee ,  Moonyoung Jeong

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device is provided. The semiconductor device includes: a lower structure including a bit line; a cell semiconductor body vertically overlapping the bit line, on the lower structure; a peripheral semiconductor body including a portion disposed on a same level as at least a portion of the cell semiconductor body, on the lower structure; and a peripheral gate on the peripheral semiconductor body, wherein the peripheral semiconductor body includes a lower region having a first width and an upper region having a second width, greater than the first width on the lower region.

公开(公告)号：US20240023311A1

公开(公告)日：2024-01-18

申请号：US18178401

申请日：2023-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho Lee ,  Moonyoung Jeong ,  Hyungjun Noh

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H10B12/05

Abstract: A semiconductor device includes a vertical pattern including a first source/drain region, a second source/drain region having a height higher than a height of the first source/drain region, and a vertical channel region between the first and second source/drain regions, a gate structure facing a first side surface of the vertical pattern, and a back gate structure facing a second side surface, opposite to the first side surface of the vertical pattern. The gate structure includes a gate electrode on the first side surface of the vertical pattern, and a gate dielectric layer including a portion disposed between the vertical pattern and the gate electrode. The back gate structure includes a back gate electrode on the second side surface of the vertical pattern, and a dielectric structure including a portion disposed between the vertical pattern and the back gate electrode. The dielectric structure includes an air gap.

公开(公告)号：US20230354582A1

公开(公告)日：2023-11-02

申请号：US18062825

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Byeongjoo Ku ,  Keunnam Kim ,  Wonsok Lee ,  Moonyoung Jeong ,  Min Hee Cho

IPC: H01L29/94

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.

公开(公告)号：US20230320077A1

公开(公告)日：2023-10-05

申请号：US18187229

申请日：2023-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moonyoung Jeong ,  Kiseok Lee ,  Sangho Lee ,  Hyungjun Noh

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/36 ,  H10B12/482 ,  H10B12/488 ,  H01L23/5283 ,  H10B12/485

Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure on the substrate, a single back gate structure between the first gate structure and the second gate structure, a first structure including a first vertical channel region extending in a vertical direction, at least a portion of the first vertical channel region between the first gate structure and the single back gate structure, and a second structure including a second vertical channel region extending in the vertical direction. The second structure is spaced apart from the first structure, and at least a portion of the second vertical channel region is between the second gate structure and the single back gate structure.

公开(公告)号：US20230178505A1

公开(公告)日：2023-06-08

申请号：US18050497

申请日：2022-10-28

Applicant: Samsung Electronics Co.. Ltd.

Inventor： KISEOK LEE ,  Hyungeun Choi ,  Gijae Kang ,  Keunnam Kim ,  Soobin Yim ,  Moonyoung Jeong ,  Seungjae Jung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H10B12/00

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/80 ,  H01L25/50 ,  H01L27/10805 ,  H01L27/10897 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: Semiconductor memory devices may include a cell array structure that may include a memory cell array including three-dimensionally arranged memory cells and first bonding pads connected to the memory cell array and a peripheral circuit structure that may include peripheral circuits and second bonding pads bonded to the first bonding pads. The cell array structure may include a lower dielectric layer having a first surface and a second surface opposite to the first surface, a stack structure including horizontal electrodes stacked in a vertical direction on the first surface of the lower dielectric layer, a vertical structure including vertical conductive patterns that extend in the vertical direction and cross the horizontal electrodes, and an input/output pad on the second surface of the lower dielectric layer.

公开(公告)号：US11540090B2

公开(公告)日：2022-12-27

申请号：US16641572

申请日：2017-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuho Han ,  Young-Sung Kho ,  Joonseo Lee ,  Moonyoung Jeong ,  Giwon Lee

IPC: H04W4/00 ,  H04W4/08 ,  H04W76/12 ,  H04W76/11 ,  H04L12/18

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure is to provide a multicast service in a wireless communication system and comprises the steps of: receiving a multicast group participation message transmitted from a terminal via a communication session from a terminal to a first network entity; generating a multicast tunnel generation request message on the basis of the multicast group participation message, and transmitting the same to the first network entity; and generating a multicast service request message on the basis of the multicast group participation message, and transmitting the same to a second network entity. The present research is research that has been conducted with the support of the “Cross-Departmental Giga KOREA Project” funded by the government (the Ministry of Science and ICT) in 2017 (No. GK17N0100, millimeter wave 5G mobile communication system development).

公开(公告)号：US10446557B2

公开(公告)日：2019-10-15

申请号：US15204805

申请日：2016-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Ji-Eun Lee ,  Kyoung-Ho Jung ,  Satoru Yamada ,  Moonyoung Jeong

IPC: H01L21/28 ,  H01L27/108 ,  H01L29/49 ,  H01L21/3215 ,  H01L29/51

Abstract: Provided are a semiconductor device having a gate and a method of forming the same. The method includes forming a gate dielectric, forming a first conductive material layer on the gate dielectric, forming a source material layer on the first conductive material layer, and diffusing a first element included in the source material layer into the first conductive material layer by performing a thermal treatment process to form a doped material layer.