公开(公告)号：US20130201758A1

公开(公告)日：2013-08-08

申请号：US13836212

申请日：2013-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doogon Kim ,  Sunil Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jaehun Jeong

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.

Abstract translation: 提供了一种操作非易失性存储器件的方法。 该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到 与第一和第二NAND串的存储单元相连的字线。

公开(公告)号：US12002764B2

公开(公告)日：2024-06-04

申请号：US17529941

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsoo Kim ,  Juyoung Lim ,  Sunil Shim ,  Wonseok Cho

IPC: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/04

CPC classification number: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/0483 ,  H01L2223/54426

Abstract: An integrated circuit device comprising a base structure, a gate stack on the base structure and comprising a plurality of gate electrodes spaced apart from each other, a first upper insulating layer on the gate stack, a plurality of channel structures that penetrate the gate stack, each of the plurality of channel structures comprises a respective alignment key protruding from the gate stack, a second upper insulating layer that overlaps the respective alignment key of each of the plurality of channel structures, a top supporting layer on the second upper insulating layer, a bit line on the top supporting layer, and a plurality of bit line contacts that electrically connect respective ones of the plurality of channel structures to the bit line. A sidewall of the first upper insulating layer includes a first step.

公开(公告)号：US11910603B2

公开(公告)日：2024-02-20

申请号：US17225493

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jesuk Moon ,  Juyoung Lim ,  Jongsoo Kim ,  Sunil Shim ,  Haemin Lee ,  Wonseok Cho

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

公开(公告)号：US20220254807A1

公开(公告)日：2022-08-11

申请号：US17507929

申请日：2021-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsoo KIM ,  Sunil Shim ,  Juyoung Lim ,  Wonseok Cho

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/528

Abstract: A semiconductor device including: a memory cell array region and a staircase region on a pattern structure; a stack structure including insulating layers and gate layers with gate pads alternately stacked in a vertical direction; a separation structure penetrating through the stack structure and contacting the pattern structure; a memory vertical structure penetrating through the stack structure and contacting the pattern structure; a support vertical structure penetrating through the stack structure and contacting the pattern structure; gate contact plugs disposed on the gate pads; and a peripheral contact plug spaced apart from the gate layers, wherein an upper surface of the memory vertical structure is at a first level, an upper surface of the peripheral contact plug is at a second level, an upper surface of the separation structure is at a third level, and upper surfaces of the gate contact plugs are at a fourth level.

公开(公告)号：US09202570B2

公开(公告)日：2015-12-01

申请号：US14142158

申请日：2013-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Woonkyung Lee ,  Wonseok Cho

IPC: H01L29/40 ,  G11C16/04 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: G11C16/0483 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional semiconductor device includes a substrate having a cell array region between first and second contact regions. A first stack includes a plurality of first electrodes vertically provided on the substrate, and a second stack includes a plurality of second electrodes vertically provided on the first stack. The second stack is arranged to expose end portions of the first electrodes on the first contact region and overlap end portions of the first electrodes on the second contact region.

Abstract translation: 三维半导体器件包括在第一和第二接触区域之间具有单元阵列区域的衬底。 第一堆叠包括垂直设置在基板上的多个第一电极，第二堆叠包括垂直设置在第一堆叠上的多个第二电极。 第二堆叠被布置成暴露第一接触区域上的第一电极的端部并且在第二接触区域上重叠第一电极的端部。

公开(公告)号：US09117923B2

公开(公告)日：2015-08-25

申请号：US13830208

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmin Hwang ,  Wonseok Cho ,  Jinsoo Lim

IPC: H01L29/792 ,  H01L27/115

CPC classification number: H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.

Abstract translation: 一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案 在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案 形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器 层，形成导电图案。

公开(公告)号：US08969162B2

公开(公告)日：2015-03-03

申请号：US13933772

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang

IPC: H01L21/336 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L21/768 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.

Abstract translation: 提供一种三维半导体器件及其制造方法。 该装置包括依次堆叠在基板上的第一电极结构和第二电极结构。 第一和第二电极结构分别包括堆叠的第一电极和堆叠的第二电极。 第一和第二电极中的每一个包括平行于基板的水平部分和从穿过基板的上表面的方向从水平部分延伸的延伸部分。 这里，衬底可以比第一电极的延伸部分的顶表面更靠近至少一个第二电极的水平部分。

公开(公告)号：US08824209B2

公开(公告)日：2014-09-02

申请号：US13836212

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doogon Kim ,  Sunil Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jaehun Jeong

IPC: G11C16/04 ,  H01L27/115 ,  H01L29/66 ,  G11C16/10 ,  H01L29/788

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.

Abstract translation: 提供了一种操作非易失性存储器件的方法。 该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到 与第一和第二NAND串的存储单元相连的字线。