公开(公告)号：US12284827B2

公开(公告)日：2025-04-22

申请号：US18473412

申请日：2023-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H10D84/83 ,  H01L21/762 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US11177364B2

公开(公告)日：2021-11-16

申请号：US16938495

申请日：2020-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Hoon Lee ,  Hoon-Joo Na ,  Sung-In Suh ,  Min-Woo Song ,  Chan-Hyeong Lee ,  Hu-Yong Lee ,  Sang-Jin Hyun

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/45 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66

Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.

公开(公告)号：US10790282B2

公开(公告)日：2020-09-29

申请号：US16229207

申请日：2018-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Jung Choi ,  Dong-Hyun Roh ,  Sung-Soo Kim ,  Gyu-Hwan Ahn ,  Sang-Jin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/308

Abstract: A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.

公开(公告)号：US10756195B2

公开(公告)日：2020-08-25

申请号：US16179250

申请日：2018-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Hoon Lee ,  Hoon-Joo Na ,  Sung-In Suh ,  Min-Woo Song ,  Chan-Hyeong Lee ,  Hu-Yong Lee ,  Sang-Jin Hyun

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/30 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/66

Abstract: Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.

公开(公告)号：US10381490B2

公开(公告)日：2019-08-13

申请号：US16040807

申请日：2018-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung Kim ,  Dong-Soo Lee ,  Sang-Yong Kim ,  Jin-Kyu Jang ,  Won-Keun Chung ,  Sang-Jin Hyun

IPC: H01L21/8234 ,  H01L29/792 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

公开(公告)号：US20180331100A1

公开(公告)日：2018-11-15

申请号：US16028272

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Lan Lee ,  Sang-Bom Kang ,  Jae-Jung Kim ,  Moon-Kyu Park ,  Jae-Yeol Song ,  June-Hee Lee ,  Yong-Ho Ha ,  Sang-Jin Hyun

IPC: H01L27/088 ,  H01L21/84 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L29/51 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

公开(公告)号：US09252058B2

公开(公告)日：2016-02-02

申请号：US14308745

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Seok Hong ,  Sang-Jin Hyun ,  Hong-Bae Park ,  Hoon-Joo Na ,  Hye-Lan Lee

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping.

Abstract translation: 制造半导体器件的方法，半导体器件和结合其的系统包括掺杂有杂质的栅极金属的晶体管。 晶体管的改变的功函数可以改变晶体管的阈值电压。 在某些实施例中，第一MOSFET的栅极金属掺杂有杂质。 第二MOSFET的栅极金属可以不掺杂，掺杂有不同浓度的相同杂质和/或掺杂有不同杂质。 在一些实施例中，MOSFET是FinFET，并且掺杂可以是共形掺杂。

公开(公告)号：US20140302652A1

公开(公告)日：2014-10-09

申请号：US14308745

申请日：2014-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung-Seok Hong ,  Sang-Jin Hyun ,  Hong-Bae Park ,  Hoon-Joo Na ,  Hye-Lan Lee

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823437 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device, a semiconductor device and systems incorporating the same include transistors having a gate metal doped with impurities. An altered work function of the transistor may alter a threshold voltage of the transistor. In certain embodiments, a gate metal of a first MOSFET is doped with impurities. A gate metal of a second MOSFET may be left undoped, doped with the same impurities with a different concentration, and/or doped with different impurities. In some embodiments, the MOSFETs are FinFETs, and the doping may be a conformal doping

Abstract translation: 制造半导体器件的方法，半导体器件和结合其的系统包括掺杂有杂质的栅极金属的晶体管。 晶体管的改变的功函数可以改变晶体管的阈值电压。 在某些实施例中，第一MOSFET的栅极金属掺杂有杂质。 第二MOSFET的栅极金属可以不掺杂，掺杂有不同浓度的相同杂质和/或掺杂有不同杂质。 在一些实施例中，MOSFET是FinFET，并且掺杂可以是共形掺杂

公开(公告)号：US20240014209A1

公开(公告)日：2024-01-11

申请号：US18473412

申请日：2023-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyu-Hwan Ahn ,  Sung-Soo Kim ,  Chae-Ho Na ,  Dong-Hyun Roh ,  Sang-Jin Hyun

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0642 ,  H01L29/785 ,  H01L29/66545

Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

公开(公告)号：US11411124B2

公开(公告)日：2022-08-09

申请号：US17134611

申请日：2020-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Jung Kim ,  Dong-Soo Lee ,  Sang-Yong Kim ,  Jin-Kyu Jang ,  Won-Keun Chung ,  Sang-Jin Hyun

IPC: H01L21/28 ,  H01L29/792 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/10 ,  B82Y10/00 ,  H01L29/786 ,  H01L27/088

Abstract: A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.