公开(公告)号：US20170025416A1

公开(公告)日：2017-01-26

申请号：US15067705

申请日：2016-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Jong-Min Lee ,  Dong-Wan Kim ,  Ju-Ik Lee

IPC: H01L27/108 ,  H01L29/423 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L28/60 ,  H01L28/86 ,  H01L29/4236

Abstract: A capacitor structure includes a plurality of lower electrodes, a support pattern structure, a dielectric layer, and an upper electrode. The lower electrodes are formed on a substrate. The support pattern structure is formed between the lower electrodes, and includes a lower support pattern and an upper support pattern structure over the lower support pattern. The upper support pattern structure includes a plurality of upper support patterns spaced apart from each other in a direction substantially perpendicular to a top surface of the substrate. The dielectric layer is formed on the lower electrodes and the support pattern structure. The upper electrode is formed on the dielectric layer. A sum of thicknesses of the plurality of upper support patterns in the direction substantially perpendicular to the top surface of the substrate is about 35% to about 85% of a total thickness of the upper support pattern structure.

Abstract translation: 电容器结构包括多个下电极，支撑图案结构，电介质层和上电极。 下电极形成在基板上。 支撑图案结构形成在下电极之间，并且在下支撑图案上方包括下支撑图案和上支撑图案结构。 上支撑图案结构包括在基本上垂直于基板的顶表面的方向上彼此间隔开的多个上支撑图案。 电介质层形成在下电极和支撑图案结构上。 上电极形成在电介质层上。 多个上支撑图案在基本上垂直于基板顶表面的方向上的厚度之和为上支撑图案结构的总厚度的约35％至约85％。

公开(公告)号：US09379002B2

公开(公告)日：2016-06-28

申请号：US14554113

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Ju-Ik Lee

IPC: H01L21/00 ,  H01L21/764 ,  H01L27/108 ,  H01L23/532 ,  G11C7/18

CPC classification number: G11C5/063 ,  G11C7/18 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

Abstract translation: 半导体器件包括位于半导体衬底上的位线结构，位线在位线结构的第一侧表面上的外部位线间隔件，内部位线间隔件包括位于位线结构和外部位之间的第一部分 并且位于半导体衬底和外部位线间隔物之间​​的第二部分和位于外部位线间隔物和内部位线间隔物的第二部分之间的块位线间隔件。 第一气隙由外部位线间隔件，内部位线间隔件和块位线间隔件限定。

公开(公告)号：US11948882B2

公开(公告)日：2024-04-02

申请号：US17964244

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53266

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US11670559B2

公开(公告)日：2023-06-06

申请号：US17206295

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung Choi ,  Jung-Hoon Han ,  Jiho Kim ,  Young-Yong Byun ,  Yeonjin Lee ,  Jihoon Chang

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L23/58 ,  H01L23/29 ,  H01L21/78

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L21/78 ,  H01L23/291 ,  H01L23/296 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/0219 ,  H01L2224/0221 ,  H01L2224/02181 ,  H01L2224/05541 ,  H01L2224/05553

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

公开(公告)号：US11495533B2

公开(公告)日：2022-11-08

申请号：US17153963

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon Chang ,  Jimin Choi ,  Yeonjin Lee ,  Hyeon-Woo Jang ,  Jung-Hoon Han

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US10665557B2

公开(公告)日：2020-05-26

申请号：US15997338

申请日：2018-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Sungjin Kim ,  Junyong Noh ,  Heonjun Lim

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/66 ,  H01L21/78 ,  H01L23/31 ,  H01L21/683

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.

公开(公告)号：US20200091100A1

公开(公告)日：2020-03-19

申请号：US16418036

申请日：2019-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Dongho Kim ,  Jaewon Seo

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/67

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

公开(公告)号：US20190035750A1

公开(公告)日：2019-01-31

申请号：US15997338

申请日：2018-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Sungjin KIM ,  Junyong NOH ,  Heonjun LIM

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/66 ,  H01L21/78

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.

公开(公告)号：US09824726B2

公开(公告)日：2017-11-21

申请号：US15164442

申请日：2016-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Dong-Wan Kim ,  Ju-Ik Lee

IPC: H01L21/00 ,  G11C5/06 ,  H01L21/764 ,  H01L27/108 ,  H01L23/528 ,  H01L23/535 ,  H01L27/105 ,  H01L23/532 ,  G11C7/18

CPC classification number: G11C5/063 ,  G11C7/18 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

公开(公告)号：US20170098619A1

公开(公告)日：2017-04-06

申请号：US15284921

申请日：2016-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Kyehee Yeom

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/06155 ,  H01L2224/06158 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same are provided. The semiconductor chip includes an integrated circuit on a substrate, a pad electrically connected to the integrated circuit, a lower insulating structure having a contact hole exposing the pad, and a conductive pattern including a contact portion filling the contact hole, a conductive line portion provided on the lower insulating structure to extend in a specific direction, and a bonding pad portion. The contact portion has a first thickness in a direction substantially perpendicular to a top surface of the substrate and a second thickness in another direction substantially parallel to the top surface of the substrate, the first thickness is greater than the second thickness, and the lower insulating structure includes a plurality of air gaps formed therein.