公开(公告)号：US10056339B2

公开(公告)日：2018-08-21

申请号：US15628349

申请日：2017-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeon-Woo Jang ,  Junghwan Park ,  Ramakanth Kappaganthu ,  Sungjin Kim ,  Junyong Noh ,  Jung-Hoon Han ,  Seung Soo Kim ,  Sungjin Kim ,  Sojung Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L2924/3512

Abstract: A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer is on the substrate and includes a pad region and a peripheral region adjacent to the pad region. The data storage elements are on the pad region of the first insulation layer. The contact plug penetrates the first insulation layer on the peripheral region. The first dummy dam penetrates the first insulation layer and is disposed between the data storage elements and the contact plug.

公开(公告)号：US11776894B2

公开(公告)日：2023-10-03

申请号：US16848246

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

IPC: H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/065 ,  H01L21/76 ,  H01L23/525 ,  H01L21/78 ,  H01L21/82 ,  H01L23/528 ,  H01L21/56

CPC classification number: H01L23/5222 ,  H01L21/561 ,  H01L21/76832 ,  H01L21/78 ,  H01L21/82 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/05 ,  H01L23/562 ,  H01L2224/024 ,  H01L2224/0237

Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

公开(公告)号：US11139199B2

公开(公告)日：2021-10-05

申请号：US16420328

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Seokhwan Kim ,  Joodong Kim ,  Junyong Noh ,  Jaewon Seo

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

公开(公告)号：US20210057328A1

公开(公告)日：2021-02-25

申请号：US16848246

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

公开(公告)号：US11984349B2

公开(公告)日：2024-05-14

申请号：US17482796

申请日：2021-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Han ,  Seokhwan Kim ,  Joodong Kim ,  Junyong Noh ,  Jaewon Seo

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76829 ,  H01L23/562

Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

公开(公告)号：US11756843B2

公开(公告)日：2023-09-12

申请号：US17706401

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Choi ,  Junyong Noh ,  Yeonjin Lee ,  Junghoon Han

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L22/34 ,  H01L21/78 ,  H01L22/32

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

公开(公告)号：US11721055B2

公开(公告)日：2023-08-08

申请号：US17333278

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Junyong Noh ,  Kyungmin Cho ,  Chaelin Kim

IPC: G06T13/40 ,  G06F16/43 ,  G06N3/08 ,  G06T13/80

CPC classification number: G06T13/40 ,  G06F16/43 ,  G06N3/08 ,  G06T13/80

Abstract: A character animation motion control method and device are disclosed. A character animation playing method, including extracting first actions based on a state of a character, extracting second actions based on the state, selecting an action included in the first actions and the second actions, and updating the state based on the action.

公开(公告)号：US20230230915A1

公开(公告)日：2023-07-20

申请号：US18127342

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin Lee ,  Junyong Noh ,  Minjung Choi ,  Junghoon Han ,  Yunrae Cho

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L21/82 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/5222 ,  H01L23/3185 ,  H01L24/05 ,  H01L23/5283 ,  H01L23/481 ,  H01L23/53295 ,  H01L21/76832 ,  H01L23/485 ,  H01L23/5226 ,  H01L21/82 ,  H01L21/561 ,  H01L21/78 ,  H01L23/562 ,  H01L2224/0237 ,  H01L2224/024

Abstract: A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

公开(公告)号：US11342235B2

公开(公告)日：2022-05-24

申请号：US16898943

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung Choi ,  Junyong Noh ,  Yeonjin Lee ,  Junghoon Han

IPC: H01L21/78 ,  H01L21/66

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

公开(公告)号：US10665557B2

公开(公告)日：2020-05-26

申请号：US15997338

申请日：2018-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Han ,  Sungjin Kim ,  Junyong Noh ,  Heonjun Lim

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/66 ,  H01L21/78 ,  H01L23/31 ,  H01L21/683

Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.