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    System on chip
    22.
    发明授权
    System on chip 有权
    片上系统

    公开(公告)号：US09589955B2

    公开(公告)日：2017-03-07

    申请号：US14872774

    申请日：2015-10-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11

    CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    Abstract translation: 提供芯片系统。 片上系统（SoC）包括第一栅极线，第二栅极线和沿第一方向延伸的第三栅极线，栅极隔离区域切割第一栅极线，第二栅极线和第三栅极线并且在 在第一方向上的第二方向，形成在第二栅极线上的第一栅极接触，布置在第一栅极线和第三栅极线之间，并且电连接切割的第二栅极线，形成在第一栅极线上的第二栅极接触， 形成在第三栅极线上的第三栅极触点，电连接第二栅极触点和第三栅极触点的第一金属线以及电连接到第一栅极触点的第二金属线。

    Integrated circuits including standard cells and method of manufacturing the integrated circuits
    25.
    发明授权
    Integrated circuits including standard cells and method of manufacturing the integrated circuits 有权

    公开(公告)号：US11063033B2

    公开(公告)日：2021-07-13

    申请号：US17010128

    申请日：2020-09-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Ho Do

    IPC: H01L27/02 ,  H01L27/118 ,  G06F30/392 ,  G06F30/394

    Abstract: Provided are integrated circuits including a plurality of standard cells aligned along a plurality of rows. The integrated circuit includes first standard cells aligned on the first row and including first conductive patterns to which a first supply voltage is applied in a conductive layer and second standard cells aligned on the second row which is adjacent to the first row in the conductive layer and including second conductive patterns to which the first supply voltage is applied in the conductive layer. A pitch between the first conductive patterns and the second conductive patterns may be less than a pitch provided by single-patterning.

    SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR
    26.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR 有权

    公开(公告)号：US20210143144A1

    公开(公告)日：2021-05-13

    申请号：US17154282

    申请日：2021-01-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

    IPC: H01L27/02 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  H01L27/118 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/092 ,  G06F30/398

    Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

    Semiconductor device including a field effect transistor
    30.
    发明授权
    Semiconductor device including a field effect transistor 有权

    公开(公告)号：US10332870B2

    公开(公告)日：2019-06-25

    申请号：US15870143

    申请日：2018-01-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

    IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522 ,  G06F17/50 ,  G03F1/36 ,  H01L23/528 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/118

    Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

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