公开(公告)号：US09905559B2

公开(公告)日：2018-02-27

申请号：US15612416

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Il Bae ,  Kang-Ill Seo

IPC: H01L27/088 ,  H01L21/31 ,  H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/786 ,  H01L29/775 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer pattern is disposed on the first fin structure. The first sacrificial layer pattern includes a left portion and a right portion arranged in the first direction. A dielectric layer pattern is disposed on the first fin structure and interposed between the left and right portions of the first sacrificial layer pattern. A first active layer pattern extending in the first direction is disposed on the first sacrificial layer pattern and the dielectric layer pattern. A first gate electrode structure is disposed on a portion of the first active layer pattern. The portion of the first active layer is disposed on the dielectric layer pattern. The first gate electrode structure extends in a second direction crossing the first direction.

公开(公告)号：US20170162651A1

公开(公告)日：2017-06-08

申请号：US14961213

申请日：2015-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-DAE SUK ,  Bom-Soo Kim ,  Kang-Ill Seo

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/51 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L27/1211 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/785

Abstract: A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference of the wire pattern and extended in a second direction that is different from the first direction, a source disposed on a first side of the gate electrode, a drain disposed on a second side of the gate electrode, the source and the drain connected to the wire pattern and a gate spacer disposed on first and second sidewalls of the gate electrode, on the source and on the drain.

公开(公告)号：US09601569B1

公开(公告)日：2017-03-21

申请号：US14961378

申请日：2015-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L27/12

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/785

Abstract: A semiconductor includes a substrate including a first region and a second region, a fin extending in a first direction in the first region of the substrate, wherein the fin includes a first semiconductor pattern and a second semiconductor pattern that are disposed on each other, a first wire pattern extending in a second direction in the second region of the substrate, a first gate electrode disposed on the fin, wherein the first gate electrode extends in a third direction that is different from the first direction, and a second gate electrode surrounding an outer perimeter of the first wire pattern and extending in a fourth direction that is different from the second direction.

公开(公告)号：US09425259B1

公开(公告)日：2016-08-23

申请号：US14802898

申请日：2015-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.

Abstract translation: 提供一种半导体器件。 半导体器件包括沿第一方向设置在衬底上的翅片。 牺牲层设置在翅片上。 有源层设置在牺牲层上。 沿着与第一方向相交的第二方向设置栅极绝缘层和栅电极。 栅极绝缘层覆盖有源层的大致整个顶部，侧面和底部表面。 源极或漏极区域设置在衬底上的栅电极的至少一侧上。 在第一区域和第二区域中的第一区域和第二区域中的锗的第一浓度高于设置在第一区域和第二区域之间的第三区域中的第二浓度的锗。

公开(公告)号：US09397179B1

公开(公告)日：2016-07-19

申请号：US14624098

申请日：2015-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Ill Seo

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0669 ,  H01L29/41733 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device including an active region having a field insulating layer disposed at a first side thereof; a first wire pattern formed on the active region and extended in a first direction; a normal gate formed on the active region, extended in a second direction crossing the first direction and covering the first wire pattern; and a dummy gate having a first part which overlaps a first end of the field insulating layer and a second part which overlaps the active region, and wherein the dummy gate is formed on the active region and spaced apart from the normal gate in the first direction, wherein the first wire pattern penetrates a third part of the dummy gate and the dummy gate covers a first end of the first wire pattern.

Abstract translation: 一种半导体器件，包括具有设置在其第一侧的场绝缘层的有源区; 形成在所述有源区上并沿第一方向延伸的第一布线图案; 形成在所述有源区上的正常栅极，沿与所述第一方向交叉的第二方向延伸并覆盖所述第一布线图案; 以及具有与所述场绝缘层的第一端重叠的第一部分的虚拟栅极和与所述有源区域重叠的第二部分，并且其中所述伪栅极形成在所述有源区上并且沿所述第一方向与所述正常栅极间隔开 ，其中所述第一布线图案穿透所述伪栅极的第三部分，并且所述伪栅极覆盖所述第一布线图案的第一端。

公开(公告)号：US20250159928A1

公开(公告)日：2025-05-15

申请号：US18732713

申请日：2024-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Kang-Ill Seo

IPC: H01L29/417 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Stacked field-effect transistor (FET) devices are provided. A stacked FET device includes a lower FET having a lower gate structure. The stacked FET device includes a contact that is electrically connected to the lower FET. The stacked FET device includes an upper FET that is on top of the lower FET. The upper FET includes an upper gate structure that includes a conductive gate and an isolation region that is in the conductive gate and on a sidewall of the contact. Moreover, the stacked FET device includes an insulating layer that is between a lower surface of the isolation region and an upper surface of the lower gate structure. Related methods of forming stacked FET devices are also provided.

公开(公告)号：US09923058B2

公开(公告)日：2018-03-20

申请号：US15196209

申请日：2016-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/1054 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: Provided is a semiconductor device. The semiconductor device includes a fin disposed on a substrate along a first direction. A sacrificial layer is disposed on the fin. An active layer is disposed on the sacrificial layer. A gate insulating layer and a gate electrode are disposed along a second direction intersecting the first direction. The gate insulating layer covers substantially entire top, side and bottom surfaces of the active layer. A source or drain region is disposed on at least one side of the gate electrode on the substrate. A first concentration of germanium in a first region and a second region of the active layer is higher than a second concentration of germanium in a third region disposed between the first region and the second region.

公开(公告)号：US09755034B2

公开(公告)日：2017-09-05

申请号：US14923982

申请日：2015-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Kwon Kim ,  Kang-Ill Seo

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/785

Abstract: A semiconductor device is provided as follows. A first nanowire is disposed on a substrate. The first nanowire is extended in a first direction and spaced apart from the substrate. A gate electrode surrounds a periphery of the first nanowire. The gate electrode is extended in a second direction intersecting the first direction. A gate spacer is formed on a sidewall of the gate electrode. The gate spacer includes an inner sidewall and an outer sidewall facing each other. The inner sidewall of the gate spacer faces the sidewall of the gate electrode. An end portion of the first nanowire is protruded from the outer sidewall of the gate spacer. A source/drain epitaxial layer is disposed on at least one side of the gate electrode. The source/drain is connected to the protruded end portion of the first nanowire.

公开(公告)号：US09754660B2

公开(公告)日：2017-09-05

申请号：US14946258

申请日：2015-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jin Kwon ,  Kang-Ill Seo

IPC: H01L27/11 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: Provided are a semiconductor device. The semiconductor device includes an SRAM cell including a first pull-up transistor, a first pull-down transistor and a first pass transistor formed on a substrate, a first read buffer transistor connected to gate terminals of the first pull-up transistor and the first pull-down transistor, and a second read buffer transistor which shares a drain terminal with the first read buffer transistor, wherein the first read buffer transistor includes a first channel pattern extending in a first direction vertical to an upper surface of the substrate, a first gate electrode which covers a part of the first channel pattern, and a first drain pattern which does not contact the first gate electrode, and which extends in the first direction, and which is electrically connected to the first channel pattern.

公开(公告)号：US09735157B1

公开(公告)日：2017-08-15

申请号：US15073908

申请日：2016-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwan-Young Chun ,  Yoon-Moon Park ,  Kang-Ill Seo ,  Wouns Yang

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088

Abstract: A semiconductor device includes a first active area, a second active area and a first gate line. The second active area is spaced apart from the first active area. The first gate line includes a first gate part crossing the first active area along a first imaginary line, a second gate part crossing the second active area along a second imaginary line, and a third gate part connecting the first gate part and the second gate part and extending along a third imaginary line crossing the first imaginary line and the second imaginary line. The first gate part, the second gate part and the third gate part are arranged so that the first gate line has a shape of 180° rotational symmetry. A point of the rotational symmetry is located on the first gate part.