公开(公告)号：US20150070643A1

公开(公告)日：2015-03-12

申请号：US14195051

申请日：2014-03-03

Applicant: Samsung Display Co., Ltd.

Inventor： Jae-Neung Kim ,  Yu-Gwang Jeong ,  Sang-Gab Kim ,  Su-Bin Bae ,  Shin-Il Choi

IPC: H01L27/12 ,  G02F1/1343

CPC classification number: H01L27/1225 ,  G02F1/134309 ,  G02F1/136213 ,  G02F2201/50 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259

Abstract: A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.

Abstract translation: 显示装置包括：限定晶体管和布线区域的基板; 晶体管区域中的薄膜晶体管，并且包括栅电极，有源层以及源极和漏极; 晶体管区域中的防蚀层，在布线区域中不存在并覆盖有源层，以及限定在防蚀层中的第一和第二接触孔，有源层电耦合到源电极和漏电极; 布线区域中的第一布线层; 覆盖所述栅电极和所述第一布线层的第一绝缘层和限定在所述布线区域中的所述第一绝缘层中的第三接触孔，并暴露所述第一布线层; 以及在所述第一绝缘层和所述布线区域中的第二布线层，并且经由所述第三接触孔电耦合到所述第一布线层。

公开(公告)号：US08853703B2

公开(公告)日：2014-10-07

申请号：US13830269

申请日：2013-03-14

Applicant: Samsung Display Co., Ltd.

Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

IPC: H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L31/0376 ,  H01L31/20 ,  H01L31/062 ,  H01L31/113 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

公开(公告)号：US20140167040A1

公开(公告)日：2014-06-19

申请号：US14184361

申请日：2014-02-19

Applicant: Samsung Display Co., Ltd.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。 源电极和漏电极彼此面对。 源电极和漏电极分别位于氧化物半导体的两个相对侧。 低导电区域位于源电极或漏电极与氧化物半导体之间。 绝缘层位于氧化物半导体和低导电区域上。 栅电极位于绝缘层上。 绝缘层覆盖氧化物半导体和低导电区域。 低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

公开(公告)号：US12087865B2

公开(公告)日：2024-09-10

申请号：US18176454

申请日：2023-02-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H10K59/121

CPC classification number: H01L29/78633 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H10K59/1213

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US11937472B2

公开(公告)日：2024-03-19

申请号：US17445471

申请日：2021-08-19

Applicant: Samsung Display Co., Ltd. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Sang Gab Kim ,  Hyun Min Cho ,  Tae Sung Kim ,  Yu-Gwang Jeong ,  Su Bin Bae ,  Jin Seock Kim ,  Sang Gyun Kim ,  Hyo Min Ko ,  Kil Won Cho ,  Hansol Lee

IPC: H10K59/131 ,  H10K59/12 ,  H10K71/00 ,  H10K102/00

CPC classification number: H10K59/131 ,  H10K59/1201 ,  H10K71/00 ,  H10K2102/341

Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.

公开(公告)号：US11756964B2

公开(公告)日：2023-09-12

申请号：US17212812

申请日：2021-03-25

Applicant: Samsung Display Co., Ltd.

Inventor： Dae Soo Kim ,  Yu-Gwang Jeong ,  Sung Won Cho

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L27/1251 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/78663

Abstract: A method for etching an insulating layer includes: sequentially forming a first gate insulating layer, an amorphous silicon layer, a first interlayer insulating layer, and a second interlayer insulating layer on a substrate; applying a photoresist on the second interlayer insulating layer, and patterning the photoresist through a photo-process; first etching the second interlayer insulating layer and the first interlayer insulating layer until at least a portion of the amorphous silicon layer is exposed by using the patterned photoresist as a mask; second etching the second interlayer insulating layer and the first interlayer insulating layer; third etching the amorphous silicon layer; and fourth etching the first gate insulating layer, wherein an etching gas used in the second etching includes a material having a higher etching selection ratio of the first and second interlayer insulating layers to the amorphous silicon layer than an etching gas used in the first etching.

公开(公告)号：US11422654B2

公开(公告)日：2022-08-23

申请号：US17344299

申请日：2021-06-10

Applicant: Samsung Display Co., Ltd.

Inventor： Daewon Choi ,  Yunjong Yeo ,  Yu-Gwang Jeong ,  Sungwon Cho

IPC: G06F3/041 ,  H01L51/52 ,  H01L27/32 ,  G06F3/044

Abstract: An electronic device includes a display panel including a plurality of pixels. A first detection insulating layer is disposed on the display panel. A first conductive pattern is disposed on the first detection insulating layer. A compensation pattern is disposed on the first detection insulating layer. A second detection insulating layer is disposed on the first detection insulating layer and covers the first detection insulating layer, the compensation pattern and the first conductive pattern. A second conductive pattern is disposed on the second detection insulating layer. The first conductive pattern includes a lower surface in contact with the first detection insulating layer. An upper surface faces the lower surface and contacts the second detection insulating layer. Lateral side surfaces extend between the lower surface and the upper surface. The compensation pattern contacts the lateral side surfaces of the first conductive pattern.

公开(公告)号：US11183518B2

公开(公告)日：2021-11-23

申请号：US16987952

申请日：2020-08-07

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang Jeong ,  Hyun Min Cho ,  Su Bin Bae ,  Shin Il Choi ,  Sang Gab Kim

IPC: H01L27/12 ,  H01L21/311 ,  H01L29/417 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32

Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

公开(公告)号：US11101336B2

公开(公告)日：2021-08-24

申请号：US16260293

申请日：2019-01-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yu-Gwang Jeong ,  Su Bin Bae ,  Joon Geol Lee ,  Sang Gab Kim ,  Shin Il Choi

IPC: H01L29/08 ,  H01L27/32 ,  H01L29/786 ,  H01L29/45 ,  H01L29/417 ,  H01L27/12

Abstract: A display device and a method for manufacturing a display device, the device including a semiconductor layer on a substrate; a gate insulation layer and an interlayer insulation layer that overlap the semiconductor layer; contact holes that penetrate the gate insulation layer and the interlayer insulation layer; a source electrode and a drain electrode that are electrically connected with the semiconductor layer through the contact holes; a light emitting diode that is connected with the drain electrode; and first spacers and second spacers between the source electrode and the interlayer insulation layer and between the drain electrode and the interlayer insulation layer in the contact holes.

公开(公告)号：US20170200747A1

公开(公告)日：2017-07-13

申请号：US15392888

申请日：2016-12-28

Applicant: Samsung Display Co., Ltd.

Inventor： Tae An Seo ,  Su Bin Bae ,  Yu-Gwang Jeong ,  Hyun Min Cho ,  Shin Il Choi ,  Jin Hwan Choi

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7869

Abstract: A TFT array panel of a display device includes a first substrate, a first electrode disposed on the first substrate, a first insulating layer including a first hole, the first insulating layer disposed on the first electrode, a second insulating layer disposed on the first insulating layer and including a second hole corresponding to the first hole, and a capping layer including a first inner portion, the capping layer disposed on an inner lateral surface forming the second hole, where an end portion of the first inner portion disposed in the second hole is separated from the first electrode.