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    Thin film transistor array panel and method of manufacturing the same
    2.
    发明授权
    Thin film transistor array panel and method of manufacturing the same 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US09153603B2

    公开(公告)日：2015-10-06

    申请号：US14105048

    申请日：2013-12-12

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ji-Young Park ,  Dong Il Kim ,  Sang Gab Kim

    IPC: H01L21/00 ,  H01L27/12

    CPC classification number: H01L27/124 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/1248 ,  H01L27/1259

    Abstract: A thin film transistor array panel includes a substrate; a gate line located over the substrate and including a gate pad portion; a data line located over the gate line and including a source electrode and a data pad portion; a drain electrode; a first passivation layer located over the data line and the drain electrode; an organic insulating layer located over the first passivation layer and having a contact hole; a first field generating electrode located over the organic insulating layer and having an opening; a second passivation layer located over the first field generating electrode; and a second field generating electrode located over the second passivation layer. The contact hole coincides with or is smaller than the opening, and the contact hole has a tapered structure.

    Abstract translation: 薄膜晶体管阵列面板包括基板; 栅极线，位于衬底上并包括栅极焊盘部分; 位于栅极线上方并包括源电极和数据焊盘部分的数据线; 漏电极; 位于数据线和漏电极之上的第一钝化层; 位于所述第一钝化层上并具有接触孔的有机绝缘层; 位于所述有机绝缘层上方并具有开口的第一场产生电极; 位于第一场产生电极之上的第二钝化层; 以及位于第二钝化层上方的第二场产生电极。 接触孔与开口重合或小于开口，接触孔具有锥形结构。

    Thin film transistor array panel
    3.
    发明授权
    Thin film transistor array panel 有权
    薄膜晶体管阵列面板

    公开(公告)号：US08853703B2

    公开(公告)日：2014-10-07

    申请号：US13830269

    申请日：2013-03-14

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

    IPC: H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L29/10 ,  H01L31/0376 ,  H01L31/20 ,  H01L31/062 ,  H01L31/113 ,  H01L29/786 ,  H01L29/66

    CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

    Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

    Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20140117361A1

    公开(公告)日：2014-05-01

    申请号：US13830269

    申请日：2013-03-14

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

    Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

    Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

    Display substrate and method of manufacturing the same
    5.
    发明授权
    Display substrate and method of manufacturing the same 有权
    显示基板及其制造方法

    公开(公告)号：US09064750B2

    公开(公告)日：2015-06-23

    申请号：US13869697

    申请日：2013-04-24

    Applicant: Samsung Display Co., LTD.

    Inventor： Yu-Gwang Jeong ,  Ji-Young Park ,  Shin-Il Choi ,  Sang-Gab Kim

    IPC: H01L29/786 ,  H01L27/13 ,  G02F1/1345 ,  H01L27/12 ,  G02F1/1337 ,  H01L33/02

    CPC classification number: H01L27/124 ,  G02F1/133707 ,  H01L27/1248 ,  H01L27/1288

    Abstract: A method of manufacturing a display substrate includes forming a gate insulation layer on the base substrate on which a gate metal pattern, forming a data metal pattern on the gate insulation layer, sequentially forming a insulation layer and an organic layer on the base substrate on which the data metal pattern is formed, partially exposing the organic layer, developing the organic layer to partially remove the organic layer on the data metal pattern and to expose at least a portion of the protecting layer on the gate metal pattern, forming a common electrode on the organic layer, forming a pixel electrode on the on the organic layer, and forming an insulation layer between the pixel electrode and the common electrode. An etching degree of a data metal may be controlled by controlling a thickness of a remained organic layer to reduce a damage of the data metal.

    Abstract translation: 一种制造显示基板的方法包括在基底基板上形成栅极绝缘层，栅基金属图案在栅绝缘层上形成数据金属图案，在基底基板上依次形成绝缘层和有机层， 形成数据金属图案，部分地暴露有机层，显影有机层以部分地去除数据金属图案上的有机层，并暴露栅极金属图案上的保护层的至少一部分，形成公共电极 有机层，在有机层上形成像素电极，在像素电极和公共电极之间形成绝缘层。 可以通过控制剩余的有机层的厚度来减少数据金属的损伤来控制数据金属的蚀刻程度。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20150072484A1

    公开(公告)日：2015-03-12

    申请号：US14487300

    申请日：2014-09-16

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

    IPC: H01L27/12 ,  H01L29/66

    CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

    Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

    Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

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