公开(公告)号：US20200208279A1

公开(公告)日：2020-07-02

申请号：US16545927

申请日：2019-08-20

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation Sungkyunkwan University

Inventor： Taejin Park ,  Jinbum Kim ,  Hyoungsub Kim

IPC: C25B11/02 ,  C25B1/04 ,  C25B11/04

Abstract: Disclosed herein are devices for hydrogen production and methods of fabricating hydrogen catalyst layers. The method may comprise forming on a substrate a first horizontal crystal and a first standing crystal that include each molybdenum oxide; forming a second horizontal crystal, a second standing crystal, and a preliminary layer on the second horizontal and standing crystals by supplying a sulfur gas onto the first horizontal crystal and the first standing crystal, the preliminary layer including molybdenum disulfide (MoS2); and removing the second horizontal crystal and the second standing crystal.

公开(公告)号：US20250169064A1

公开(公告)日：2025-05-22

申请号：US18735338

申请日：2024-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bitna Kim ,  Jinbum Kim ,  Kyeonggyu Lee ,  Sunguk Jang ,  Sunghwan Jang ,  Wonhee Choi

IPC: H10B12/00

Abstract: A semiconductor device includes a bit line on a substrate, a channel on the bit line, a first gate structure on a first sidewall of the channel, a contact structure between the bit line and the channel, the contact structure contacting the bit line and the channel, the contact structure including: a first contact including a semiconductor material doped with first impurities, the first impurities including a first diffusion coefficient, and a second contact on the first contact, the second contact contacting the first contact, the second contact including a semiconductor material doped with second impurities, the second impurities including a second diffusion coefficient, the second diffusion coefficient being less than the first diffusion coefficient, and a capacitor on and electrically connected to the channel.

公开(公告)号：US20250126771A1

公开(公告)日：2025-04-17

申请号：US18747624

申请日：2024-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim

IPC: H10B12/00

Abstract: A method of manufacturing a semiconductor memory device includes forming a metal seed pattern having a plurality of openings on a substrate, forming a metal silicide pattern from the substrate and the metal seed pattern, growing a single crystal semiconductor pattern in a vertical direction at an interface between the substrate and the metal silicide pattern where the vertical direction is perpendicular to the substrate, and growing a sacrificial semiconductor pattern in the vertical direction at an interface between the metal silicide pattern and the single crystal semiconductor pattern.

公开(公告)号：US12268022B2

公开(公告)日：2025-04-01

申请号：US17714695

申请日：2022-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Dahye Kim ,  Dongmyoung Kim ,  Dongwoo Kim ,  Yongjun Nam ,  Sangmoon Lee ,  Ingyu Jang ,  Sujin Jung

IPC: H10D62/10 ,  H10D62/13 ,  H10D62/17

Abstract: A semiconductor device includes a substrate having an active region extending in a first direction; a gate structure disposed on the substrate, intersecting the active region, and extending in a second direction; channel layers disposed on the active region to be spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and to be surrounded by the gate structure; source/drain regions disposed on both sides of the gate structure and connected to the channel layers; air gap regions located between the source/drain regions and the active region and spaced apart from each other in the third direction; and semiconductor layers alternately disposed with the air gap regions in the third direction and defining the air gap regions, wherein lower ends of the source/drain regions are located on a level lower than an uppermost air gap region.

公开(公告)号：US20240297215A1

公开(公告)日：2024-09-05

申请号：US18658794

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungkeun Lim ,  Unki Kim ,  Yuyeong Jo ,  Yihwan Kim ,  Jinbum Kim ,  Pankwi Park ,  Ilgyou Shin ,  Seunghun Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/0245 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

公开(公告)号：US20240266256A1

公开(公告)日：2024-08-08

申请号：US18369527

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Jinbum Kim

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: The present disclosure provides semiconductor devices including a field effect transistor (FET) and methods of fabricating the same. In some embodiments, a semiconductor device includes a substrate, a lower power line buried in a lower portion of the substrate, a source/drain pattern on the substrate, and a backside contact that penetrates the substrate and electrically couples the lower power line to the source/drain pattern. The backside contact includes an epitaxial pattern coupled to a lower portion of the source/drain pattern, a contact plug coupled to the lower power line, and a metal-semiconductor compound layer between the epitaxial pattern and the contact plug. The epitaxial pattern includes a top surface that protrudes toward the source/drain pattern.

公开(公告)号：US11990549B2

公开(公告)日：2024-05-21

申请号：US17716005

申请日：2022-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee Jung ,  Jinbum Kim ,  Dongil Bae

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device includes an active region extending from a substrate in a vertical direction, source/drain regions spaced apart from each other on the active region, a fin structure between the source/drain regions on the active region, the fin structure including a lower semiconductor region on the active region, a stack structure having alternating first and second semiconductor layers on the lower semiconductor region, a side surface of at least one of the first semiconductor layers being recessed, and a semiconductor capping layer on the stack structure, an isolation layer covering a side surface of the active region, a gate structure overlapping the fin structure and covering upper and side surfaces of the fin structure, the semiconductor capping layer being between the gate structure and each of the lower semiconductor region and stack structure, and contact plugs electrically connected to the source/drain regions.

公开(公告)号：US20240162293A1

公开(公告)日：2024-05-16

申请号：US18415765

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  DAHYE KIM ,  SEOKHOON KIM ,  JAEMUN KIM ,  Ilgyou Shin ,  Haejun YU ,  KYUNGIN CHOI ,  KIHYUN HWANG ,  SANGMOON LEE ,  SEUNG HUN LEE ,  KEUN HWI CHO

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20240145542A1

公开(公告)日：2024-05-02

申请号：US18325412

申请日：2023-05-30

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jang Ingyu ,  Jinbum Kim ,  Sujin Jung ,  Gyeom Kim ,  Dahye Kim

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern disposed on a substrate; a gate structure disposed on the active pattern; channels disposed on the substrate and that are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate; a first epitaxial layer disposed on a portion of the active pattern adjacent to the gate structure; and a contact plug disposed on the first epitaxial layer. The contact plug includes a lower portion; a middle portion disposed on the lower portion, where the middle portion has a width that increases from a bottom to a top thereof along the vertical direction; and an upper portion disposed on the middle portion.

公开(公告)号：US11881510B2

公开(公告)日：2024-01-23

申请号：US17935561

申请日：2022-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Seokhoon Kim ,  Kwanheum Lee ,  Choeun Lee ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.